Предприятие. DataPath. [Редактировать]

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#Новостная лента.
12017-01-02. Компания DataPath получила военный контракт.
Компания DataPath получила $363 млн. контракт на предоставление услуг спутниковой связи в интересах военного ведомства США. В рамках своей части работ компания поставит заказчику как оборудование так и программное обеспечение. Срок действия договора составляет 4.5 лет. Тэги: DataPathМинистерство обороны США

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... implementations in general, because the datapath contains a number of well defined... the clock frequency of the datapath module to its optimal operation... the Synchronous Circuit. If the datapath con¬ trollers within the synchronous... requirement for the syn¬ chronous datapath controllers is often smaller or...¬ a separate module to decouple the datapath accessing it. mentioned above require... is possible to retain the datapath structure unchanged, controllers must usually... controller iL A 1' if datapath H local controller datapath -«^§—!* datapath local controller •*— -* A datapath datapath datapath i n 5='®!. local controller w#q local controller i#^t local controller m^ iL »j|g i iL # datapath datapath - datapath... t ffpt t ^P\i datapath - •"oca' controller i Figure 6.30: generator) î datapath datapath A (clock generator) controlling...



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...-3 Bus Master Operation ............................................................................................ 18-3 Write Datapath ........................................................................................................... 18-4 LCDIF Interrupts ..................................................................................................... 18-10... Level Diagram ................................................................................................... 18-2 LCDIF Write DataPath.......................................................................................................... 18-6 8-Bit LCDIF Register Programming... devices consists of these fields: • • • • • Datapath Column Row Chip Select Bank...: Bank-Chip Select-Row-Column-Datapath The maximum widths of each... = 13 bits Column = 12 bits Datapath = 1 bit The actual width of... 25 13 Row 12 1 Column 0 Datapath Figure 12-4. Memory Controller Memory... Select 12 11 Row 1 Column 0 Datapath Figure 12-5. Example Memory Map... at byte address 0x1, the Datapath bit would be a 1 in order... memory word-aligned if the Datapath bit is 0. 12.2.2.2 Memory Controller... main FIFOs in the block datapath. The latency FIFO (LFIFO) is... the HW_LCDIF_CTRL1 register. 18.2.2 Write Datapath All frame buffers must be... tu s Figure 18-2. LCDIF Write DataPath The examples in Figure 18... that indicates that LCD read datapath FIFO is full, will be... that indicates that LCD write datapath FIFO is full, will be...



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... and gearbox. In the RX datapath, FEC resides between the gearbox... 4'b0000) RW 3 DATAPATH_RESET (RXG) Channel datapath reset control. Required once the.... (Resets both Tx and Rx datapath) 2 TXFIFO_RESET (G) Transmit FIFO reset control... operation. (Default 1’b0) 1 = Resets transmit datapath FIFO. 1 RXFIFO_RESET (G) Receive FIFO reset... operation. (Default 1’b0) 1 = Resets receive datapath FIFO. RESERVED For TI use... has occurred in the transmit datapath (CTC) FIFO. RO/LH 6 TX_FIFO_OVERFLOW... has occurred in the transmit datapath (CTC) FIFO. RO/LH 5 RX_FIFO_UNDERFLOW... has occurred in the receive datapath (CTC) FIFO. RO/LH 4 RX_FIFO_OVERFLOW... has occurred in the receive datapath (CTC) FIFO. In 1G-KX... RESET (RX) 1 = Global reset. Resets datapath and MDIO registers of all... data traverses through entire Tx datapath excluding HS serdes and will... Description Access 15 PCS_RESET (R) 1 = Resets datapath and MDIO registers of all...



Дата загрузки: 2016-12-29
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... modelling ...............................................................106 Modelling environment ........................................................................106 Datapath model design .........................................................................108 Control model... PC latch scheme ...................................................................................131 Control datapath design .......................................................................132 3 Evaluation of design... unit implementation .....................................................182 Arithmetic / logic datapath design .......................................................184 Multiplier Design .............................................................................185... 5.9 Looping FIFO datapath diagram 5.10 Top-level diagram of control datapath 6.1 Structure... the functional unit 8.5 Arithmetic / logic datapath structure 8.6 Signed digit Booth multiplexer..., in the section “Arithmetic / logic datapath design” on page 184. 11x7... was reduced by dividing the datapath into two eight-bit segments... additional transitions in the datapath as the datapath would be designed using... with the data in the datapath: the request signal is implicit... to the width of the datapath, which adds to both the... the processing delay in the datapath (although micropipelines can also use... particular stages, so that the datapath explicitly indicates when it has... equal to the worst case datapath delay. A typical way of doing... the same way as the datapath, avoiding the need for the... circuitry operates concurrently with the datapath, and the appropriate delay is... in how to implement the datapath parts of asynchronous circuits, it... of a pipelined 32x32 bit multiplier datapath. This multiplier consists of four.... Full-custom layout for the datapath was used, in order to... to be fed through the datapath to check correct operation. The...; and as the control and datapath functions are merged to some... dissipated by transitions within the datapath associated with the data, and... with the delays in the datapath. The broadish data validity scheme... classes: asynchronous control circuits and datapath circuits. The control circuits implement... control the operation of the datapath. The interfaces and the operation... asynchronous circuit synthesis tool [117]. Datapath circuits consist of conventional processing... modelled at a lower level, with datapath elements and asynchronous control circuits... by separate models. Some trivial datapath functions were implemented directly with... the design by specifying the datapath and control elements of the... for asynchronous control circuits and datapath elements, it was possible to.... This was done for the datapath circuits first, so that any... represented in Figure 4.1. 4.2.2 Datapath model design The datapath elements of the processor... technique used to produce skeletal datapath models. The Perl script used... Datapath models Refine high-level models Control models Datapath models Control model Datapath model Replace datapath models with... a mixture of asynchronous interfaces and datapath logic and were designed using..., the register file and the datapath components of the functional units... opens the latches in the datapath. When the write request signal...-independent logic, and the control datapath which is responsible for storing... nptr_moved setup Figure 5.9 Looping FIFO datapath diagram The main task of... latch elements. 5.2.5 Control datapath design The control datapath, as shown diagrammatically in... datapath and the reverse requests from the decode stage. The control datapath... read pointer from the FIFO datapath (encoded into 5-bit binary) is... Top-level diagram of control datapath data-dependent ripple-carry incrementer... of the address generation unit datapath are depicted in Figure 7.5. For... datapath design A simplified diagram of the structure of the arithmetic / logic datapath is shown in Figure MULTIPLIER MUX / RND 8.5. The datapath consists...:0] LOGIC b[39:0] Figure 8.5 Arithmetic / logic datapath structure Multiplication is always unsigned... of writing, all of the datapath components of the processor have... [48] L. Nielsen, J. Sparsø, “A Low Power Datapath for a FIR Filter Bank”, Proc... Micheli, “Reducing Switching Activity on Datapath Buses with Control-Signal Gating... index_unit_ctl module. This controls the datapath signals for writes to and... of the circuit is the datapath, and consists of four main... set up and how the datapath responds to signals from the...



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... top level for the read datapath. www.xilinx.com Spartan-6 FPGA... top level for the write datapath. /example_design/rtl/mcb_controller This directory... top level for the read datapath. This module stores the read... top level for the write datapath. www.xilinx.com Spartan-6 FPGA...



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... Input Data Timing Specifications ................................. 8  Digital Datapath ............................................................................. 65  Latency Variation Specifications ................................................ 9  DAC... Configuration and Function Descriptions ........................... 12  Datapath PRBS ........................................................................... 69  Terminology .................................................................................... 15  DC... Power Dissipation.............................................................. 78  Step 2: Digital Datapath ............................................................. 27  Temperature Sensor ................................................................... 78  Step... Link Layer .............................................................. 28  Step 2: Digital Datapath............................................................. 79  Step 6: Optional Error Monitoring... input data rate. The digital datapath of the AD9135/AD9136 offers.../AD9136 (see the Step 2: Digital Datapath section). Set up the JESD204B... 0xFF 0x01 Description Digital datapath configuration Digital datapath configuration Clock configuration SERDES... Sheet AD9135/AD9136 STEP 2: DIGITAL DATAPATH Table 19. Transport Layer Settings... 3 DualLink 2 CurrentLink Table 18. Digital Datapath Settings Addr. 0x112 Bit No... be enabled during the Digital Datapath configuration step, or after the.... Data Sheet AD9135/AD9136 DIGITAL DATAPATH INV SINC DIGITAL GAIN, DC... 73. Block Diagram of Digital Datapath The block diagram in Figure... the functionality of the digital datapath (all blocks can be bypassed... pipeline delay changes when digital datapath functions are enabled/disabled. If... initial configuration. DAC PAGING Digital datapath registers are paged to allow.... The AD9135 uses a 16-bit datapath that is truncated to 11... minimizing quantization error along the datapath. The usable bandwidth (as shown... gain, dc offset, group delay, datapath PRBS, and LMFC sync. The... the DAC and flushes the datapath. The BSM is activated by... the DAC and flushes the datapath. On a falling edge of TX_PROTECT... by the Tx ENSM), the datapath holds the latest data value... 0. At the same time, the datapath is flushed with zeros. On... allowed to flow through the datapath again and the digital gain... Sets SPI_PROTECT Inverts PROTECT_OUTx DATAPATH PRBS The datapath PRBS can be used to verify that the AD9135/ AD9136 datapath is receiving and correctly decoding data. The datapath PRBS verifies... has been implemented correctly. The datapath PRBS test is designed to... up to 1060 MHz. The datapath PRBS is paged as described... Paging section. To run the datapath PRBS test, complete the following... PRBS as described in the Datapath PRBS IRQ section. 8. If there... (3 errors) AD9135/AD9136 Data Sheet Datapath PRBS IRQ DC TEST MODE... this mode is enabled, the datapath is given 0 (midscale) for its.../AD9136 (see the Step 2: Digital Datapath section). Set up the JESD204B... 0xFF 0x01 Description Digital datapath configuration Digital datapath configuration Clock configuration SERDES... PLL locked STEP 2: DIGITAL DATAPATH Table 79. Digital Datapath Command W W Rev. A | Page... to 0x8B for proper digital datapath configuration. Must write the default... to 0x01 for proper digital datapath configuration. Blanking State. Data is...



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... followed by four 48-bit datapath multiplexers (with outputs W, X, Y, and Z). This... upper 30 bits of A:B concatenated datapath, and the 18-bit B input... lower 18 bits of the A:B datapath. The A:B datapath, together with the C input... 0, 1, or 2 pipeline stages in its datapath. The dual A, D, and pre-adder... used to gate the A or B datapath to use the pre-adder... of pipestages for the C input datapath. X-Ref Target - Figure 2-7 48 C 48... cycle (e.g., when altering the internal datapath configuration of the DSP48E2 slice...



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... ......................................................................... 31 SED Example............................................................................... 51 Digital Datapath.............................................................................. 32 Example Start-Up Routine....................................................................... 32 Derived PLL Settings ................................................................. 52 Datapath Configuration ............................................................ 34 Start-Up Sequence... Addr (Hex) 0x1B Register Name Datapath control 0x1C HB1 control 0x1D... 0x3D 0x3E 0x3F 0x40 0x41 Datapath config Chip ID I phase adj... acknowledge FIFO soft align request 1 Datapath Control 0x19 0x1B [7:0] 7 6 5 2 1 FIFO Level... disable the clocks to the Q datapath. Send I data to both the... 0 000000 0 Data Sheet Register Name Datapath Config Chip ID I Phase Adj... the block diagram of the datapath through the FIFO. The data... and fed into the digital datapath. The value of the read... data is read into the datapath from the FIFO. The FIFO... 56 AD9146 Data Sheet DIGITAL DATAPATH HB1 HB2 PHASE AND OFFSET... Diagram of Digital Datapath MODE 3 The digital datapath can also be used.... –20 MAGNITUDE (dB) The digital datapath accepts I and Q data streams and... the functionality of the digital datapath. The digital processing includes a premodulation... 80 70 60 50 40 DATAPATH CONFIGURATION –0.04 –0.06 –0.08 0 0.04...-049 –0.10 Configuring the AD9146 datapath starts with the application requirements... first step in configuring the datapath is to verify that the... dc value of the I datapath and the Q datapath can be independently controlled... are added directly to the datapath values. Care should be taken... present in the FIFO and datapath. Two different delay lengths are... receiving correct data after the datapath is flushed. The amount of... filter power-down option selected Datapath flush time = 175 DAC clocks... flush the datapath is only 238 ns. Therefore, if datapath flushing is... time needed to flush the datapath must be accounted for when... constraint determines how soon the datapath must begin to be flushed...



Дата загрузки: 2017-01-04
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... ......................................................................... 31 SED Example............................................................................... 51 Digital Datapath.............................................................................. 32 Example Start-Up Routine....................................................................... 32 Derived PLL Settings ................................................................. 52 Datapath Configuration ............................................................ 34 Start-Up Sequence... Addr (Hex) 0x1B Register Name Datapath control 0x1C HB1 control 0x1D... 0x3D 0x3E 0x3F 0x40 0x41 Datapath config Chip ID I phase adj... acknowledge FIFO soft align request 1 Datapath Control 0x19 0x1B [7:0] 7 6 5 2 1 FIFO Level... disable the clocks to the Q datapath. Send I data to both the... 0 000000 0 Data Sheet Register Name Datapath Config Chip ID I Phase Adj... the block diagram of the datapath through the FIFO. The data... and fed into the digital datapath. The value of the read... data is read into the datapath from the FIFO. The FIFO... 56 AD9146 Data Sheet DIGITAL DATAPATH HB1 HB2 PHASE AND OFFSET... Diagram of Digital Datapath MODE 3 The digital datapath can also be used.... –20 MAGNITUDE (dB) The digital datapath accepts I and Q data streams and... the functionality of the digital datapath. The digital processing includes a premodulation... 80 70 60 50 40 DATAPATH CONFIGURATION –0.04 –0.06 –0.08 0 0.04...-049 –0.10 Configuring the AD9146 datapath starts with the application requirements... first step in configuring the datapath is to verify that the... dc value of the I datapath and the Q datapath can be independently controlled... are added directly to the datapath values. Care should be taken... present in the FIFO and datapath. Two different delay lengths are... receiving correct data after the datapath is flushed. The amount of... filter power-down option selected Datapath flush time = 175 DAC clocks... flush the datapath is only 238 ns. Therefore, if datapath flushing is... time needed to flush the datapath must be accounted for when... constraint determines how soon the datapath must begin to be flushed...



Дата загрузки: 2017-01-10
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... architecture a CMD (Combined Multiplier Divider) datapath is designed which is used... negligible with respect to the datapath for all practical values of... Point Add using the CMD Datapath . . . . . 6.5.2 An FSM-type Control Unit... example, on a practical chip, the datapath logic area is just a fraction... inputs to each PE: the datapath inputs consisting of r, s, u, v, f ; the control... reduce the delay of the datapath. The sign of δ as defined... 5.1 with the exception of its datapath input set. In Figure 5.4, the... architecture, then more conveniently, the datapath input set may follow those... processor will be proposed, whose datapath is based on a combined multiplier... easily expanded independent of the datapath to provide adequate external buffering... of PEs present in the datapath. This scalability fea- CHAPTER 6. SYSTOLIC... propose an asynchronous wave pipelined datapath (multiplier) coupled with synchronous control... is being proposed. However, its datapath requires m bit buses and multiple..., register file and datapath. In Figure 6.1, the datapath is shown in two... Figure 6.2, three sets of inputs: datapath signals (R, S, U, V, F ), state signals (dec, dseq... Point Add using the CMD Datapath Considering the bit serial systolic... size, where its 256 bit datapath can run at 40 MHz... processor has been investigated whose datapath is based on a combined multiplier... of PEs present in the datapath at the expense of lower... negligible with respect to its datapath. Hence, a datapath based on a combined multiplier... rates. This unidirectional bit serial datapath structure coupled with a shift register... of PEs present in the datapath at the expense of lower...