Спутник технологический. LDREX. [Редактировать]

Японский экспериментальный антенный модуль LDREX (LargeScale Deployable Reflector Experiment) – это крупномасштабная отражательная антенна со средствами ее развертывания. Он изготовлен корпорацией Toshiba Corp. по заказу японского космического агентства NASDA. Главной целью запуска LDREX является проверка работы механизма разворачивания этой антенны в интересах программы создания и запуска в 2003 г. экспериментального японского спутника связи ETS VIII. Антенна LDREX является уменьшенной в два раза моделью двух антенн LDR (Large scale Deployable Reflector – крупномасштабный складной отражатель) на ETS VIII.

Дополнительные наименования

#НаименованияПоиск в новостяхПоиск в документах
1Large-scale Deployable Reflector EXperimentНайтиНайти
226640НайтиНайти

Дополнительная классификация

#Наименования
1Тип оператора(владельца) - государственный
2Страна производитель - Япония
3Страна оператор(владелец) - Япония

Технические характеристики

#ХарактеристикаЗначение
1Масса, кг182
2Масса (антенны), кг140
3Масса (блока электроники), кг37
4Масса (видеокамеры), кг2
5Масса (кабельной сети ), кг3
6Габариты (при запуске), метра1.8x0.7x0.7

Пусковые характеристики

#ХарактеристикаЗначение
1Код NSSDC2000-081C

Информация об удачном запуске

#ХарактеристикаЗначение
1Космодром Космодром Куру
2Дата пуска2000-12-20 at 00:26:00 UTC
3Полезная нагрузка 1xAstra 2D
4Полезная нагрузка 1xGE 8
5Полезная нагрузка 1xLDREX
6Ракета-носитель 1xАриан 5G

Найдено 143 документов по запросу «LDREX». [Перейти к поиску]


Дата загрузки: 2016-12-29
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0.2/5
... on an No fix scheduled LDREX that is preceded by a write... the exclusive monitor Description: A conditional LDREX might set the internal exclusive... conditional LDREX along with non-conditional STREX. • If no conditional LDREX is... cannot be triggered. • If conditional LDREX is used, the associated STREX... set by the condition failed LDREX, the following STREX will not... this erratum consists in using LDREX instead of standard LDR in... monitor. So, if a program executes a LDREX/STREX loop which keeps on... middle of the LDREX/STREX sequence, then the LDREX/STREX sequence never... LDREX ... DSB STREX CMP BNE loop .... LDR (into aborting region) The LDREX... now appears “before” the LDREX and DSB) LDREX DSB STREX The LDR... because it is aborting The LDREX is executed, and sets the... back on the same failing LDREX/STREX sequence. Conditions: The erratum... in the middle of the LDREX/STREX sequence, then the processor... the erratum from happening: • Usual LDREX/STREX code sequences do not... in the middle of the LDREX/STREX sequence on each iteration... the next iteration of the LDREX/STREX sequence will succeed. Workarounds... in the middle of the LDREX/STREX sequence. If a DSB is... it before the LDREX/STREX sequence, and implement the LDREX/STREX sequence...,” can be reported on an LDREX that is preceded by a write... by the execution of an LDREX instruction, can cause the “STREX... region. • The processor executes an LDREX instruction. • No DSB instruction is... response on AXI) while the LDREX is being executed, the erratum... Ordered memory region and the LDREX instruction. Proposed Solution: No fix... happen: MOV r1,#0x40 Loop: LDREX r5, [r1,#0x0] CMP r5...



Дата загрузки: 2017-06-15
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0.13/5
38 - 4 LDREX-2 18 10 25 1 LDREX-2 LDREX-2 LDREX 2 LDREX-2 • LDREX-2 10 14 5 56 18 5 • 2 10 16 • 4 10 18 • 3 LDREX-2 5 18 56 10 14 4 LDREX-2 (1) LDREX-2 ON (2) (3) (4) (5) (6) (7) LDREX-2 OFF LDREX-2 0:00 0:10 3:10 8:10 13:10 43:23 44:15 0:42:49 0:42.59 0:45:59 0:50:59 0:55:59 1:26:12 1:27:04 1:28:29 0:00 0:42:36 0:10 0:42.46 3:10 0:45:46 8:10 0:50:46 13:10 0:55:46 43:23 1:25:59 44:13 1:26:49 1:27:47 5 LDREX-2 6 (1/3) • LDREX HRM HRM 6 HRM 2 HRM 8 HRM HRM 4 10 7 (2/3) • HRM 2 13% 13% 8 (3/3) • * • 32 95% * • • 9 LDR • LDR LDREX-2 LDREX-2 LDR LDR (1/2) 32% 2 10 LDR (2/2) • LDREX-2 LDR • LDREX-2 LDR • LDREX-2 ETS- LDR 11 ETS-VIII ETS 12



Дата загрузки: 2017-06-14
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0.09/5
LDREX-2 18 LDR 8 23 ETSLDREX-2 2004 1 LDREX-2 ETS- LDR ¾ ¾ LDREX ¾ ¾ LDREX ¾ ¾ LDREX 1 LDREX LDR LDREX-2 2 LDREX 2 LDREX 3 LDR LDREX2 LDREX-2 G LDR 4 LDREX-2 „„ „„ „„ „„ „„ „„ „„ „„ 18 10 14 LDREX-2 – - 2 (B-BOX) E-BOX 1 ASAP5 ASAP5 Ariane5 Structure for Auxiliary Payloads 2m 5 LDREX-2 - - 2 1 6m 1 2 1 (9:02) 2 2 (24:44) (26:58) SYLDA (30:49) (32:02) SRB (2:20) (0:00) LDREX-2 (0:42:49 – 1:27:04) 6 LDREX-2 (1) LDREX-2 ON (2) (3) (4) (5) (6) (7) LDREX-2 OFF LDREX-2 (1) (2) 0:00 0:10 3:10 8:10 13:10 43:23 44:15 (3) 0:42:49 0:42.59 0:45:59 0:50:59 0:55:59 1:26:12 1:27:04 1:28:29 (4) (5) (6) 18 9 20 18 10 14 7



Дата загрузки: 2017-05-20
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0.16/5
... . . . . . . . . . . . . . . . 85 3.17 Atomic increment using LDREX/STREX . . . . . . . . . . . . . . . . . . 86 3.18 Assembly pseudo... as a single atomic operation using LDREX, STREX 70 the effect of...)” (Jensen et al., 1987) or LDREX/STREX in ARM parlance. LL... the time between two instructions: LDREX and STREX, which stand for...-exclusive” and “storeexclusive” respectively. The LDREX operation retrieves a word from memory... as was previously accessed by LDREX. However, if anything has disturbed... whole operation, starting with the LDREX all over again. Various effects... the number of instructions between LDREX and STREX be kept to... In short, the use of LDREX/STREX implies that the code... decision restricts the number of 1. 2. 3. 4. v ← LDREX [address] v ←v+1 r ← STREX v, [address] if r = 0 then... 1 Figure 3.17: Atomic increment using LDREX/STREX 87 bits: 2 32 p 2 2 t f 26... S; if p = t then { t ← f }; ri ← t 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. rw ← LDREX [address] rw ← rw + 1 rp ← GetBits... S = 0 and rcount [p] = 0 then { p ← t } 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. rw ← LDREX [address] rS ← GetBits (rw , 0, SLENGTH... of f , wrapped in the usual LDREX/STREX pair. For both the... post-conditions. And I know that LDREX and STREX will always allow...- 93 tion, starting from before LDREX and recording the cycle count...



Дата загрузки: 2017-01-23
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0.06/5
... region, followed by a condition-failed LDREX, might deadlock the processor No...,” can be reported on an LDREX that is preceded by a write... the exclusive monitor Description: A conditional LDREX might set the internal exclusive... conditional LDREX along with non-conditional STREX. • If no conditional LDREX is... cannot be triggered. • If conditional LDREX is used, the associated STREX... set by the condition failed LDREX, the following STREX will not... BSP does not use conditional LDREX. Chip Errata for the i.MX... monitor. So, if a program executes a LDREX/STREX loop which keeps on... middle of the LDREX/STREX sequence, then the LDREX/STREX sequence never... LDREX ... DSB STREX CMP BNE loop .... LDR (into aborting region) The LDREX... now appears “before” the LDREX and DSB) LDREX DSB STREX The LDR... because it is aborting The LDREX is executed, and sets the... back on the same failing LDREX/STREX sequence. Conditions: The erratum... in the middle of the LDREX/STREX sequence, then the processor... the erratum from happening: • Usual LDREX/STREX code sequences do not... in the middle of the LDREX/STREX sequence on each iteration... the next iteration of the LDREX/STREX sequence will succeed. Workarounds... in the middle of the LDREX/STREX sequence. If a DSB is... it before the LDREX/STREX sequence, and implement the LDREX/STREX sequence... region, followed by a condition-failed LDREX, might deadlock the processor Description... by the execution of a conditional, LDREX instruction that fails its condition... region. • The processor executes a conditional LDREX instruction. • The instruction fails its... memory region and the conditional LDREX. Proposed Solution: No fix scheduled... BSP. No conditional usage of LDREX instructions in the BSP. Chip...,” can be reported on an LDREX that is preceded by a write... by the execution of an LDREX instruction, can cause the “STREX... region. • The processor executes an LDREX instruction. • No DSB instruction is... response on AXI) while the LDREX is being executed, the erratum... Ordered memory region and the LDREX instruction. Proposed Solution: No fix... happen: MOV r1,#0x40 Loop: LDREX r5, [r1,#0x0] CMP r5...



Дата загрузки: 2017-06-15
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0.13/5
... instructions are:  The word instructions LDREX and STREX  The halfword instructions... the synchronization primitive instructions, see “LDREX and STREX” and “CLREX” . 12... Access Instructions Instruction CMSIS Function LDREX uint32_t __LDREXW (uint32_t *addr) LDREXH...] Load Register with two bytes - LDREX Rt, [Rn, #offset] Load Register... address LDRD Load Register Dual LDREX{type} Load Register Exclusive POP...} 12.6.4.8 LDREX and STREX Load and Store Register Exclusive. Syntax LDREX{cond... the value in Rn. Operation LDREX, LDREXB, and LDREXH load a word... change the flags. Examples MOV LDREX R1, #0x1 R0, [LockAddr] ; Initialize...



Дата загрузки: 2017-05-20
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0.2/5
... on an No fix scheduled LDREX that is preceded by a write... the exclusive monitor Description: A conditional LDREX might set the internal exclusive... conditional LDREX along with non-conditional STREX. • If no conditional LDREX is... cannot be triggered. • If conditional LDREX is used, the associated STREX... set by the condition failed LDREX, the following STREX will not... this erratum consists in using LDREX instead of standard LDR in... monitor. So, if a program executes a LDREX/STREX loop which keeps on... middle of the LDREX/STREX sequence, then the LDREX/STREX sequence never... LDREX ... DSB STREX CMP BNE loop .... LDR (into aborting region) The LDREX... now appears “before” the LDREX and DSB) LDREX DSB STREX The LDR... because it is aborting The LDREX is executed, and sets the... back on the same failing LDREX/STREX sequence. Conditions: The erratum... in the middle of the LDREX/STREX sequence, then the processor... the erratum from happening: • Usual LDREX/STREX code sequences do not... in the middle of the LDREX/STREX sequence on each iteration... the next iteration of the LDREX/STREX sequence will succeed. Workarounds... in the middle of the LDREX/STREX sequence. If a DSB is... it before the LDREX/STREX sequence, and implement the LDREX/STREX sequence...,” can be reported on an LDREX that is preceded by a write... by the execution of an LDREX instruction, can cause the “STREX... region. • The processor executes an LDREX instruction. • No DSB instruction is... response on AXI) while the LDREX is being executed, the erratum... Ordered memory region and the LDREX instruction. Proposed Solution: No fix... happen: MOV r1,#0x40 Loop: LDREX r5, [r1,#0x0] CMP r5...



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0.13/5
... provided are: • Load-Exclusives: LDREX, see LDREX on page A6-106 — LDREXB... primitives using, as examples, the LDREX and STREX instructions. The same... together, as a pair, for example a LDREX/STREX pair or a LDREXB/STREXB.... These notes describe use of a LDREX/STREX pair, but apply equally... is different from the preceding LDREX in the same execution thread... be UNPREDICTABLE. As a result, an LDREX/STREX pair can only be..., therefore, performing a store between the LDREX and the STREX can result... an explicit store between an LDREX and an STREX in a single... are executed without an intervening LDREX the second STREX returns a status...: — every STREX must have a preceding LDREX associated with it in a given... is not necessary for every LDREX to have a subsequent STREX. • An... an exclusive monitor between the LDREX and the STREX, without any... cache maintenance operations between the LDREX and STREX instructions. • Implementations can benefit from keeping the LDREX and STREX operations close together... state being cleared between the LDREX instruction and the STREX instruction... a limit of 128 bytes between LDREX and STREX instructions in a single... guideline rather than a functional requirement. • LDREX and STREX operations must be... by an LDREX/STREX pair are changed between the LDREX and the...-Exclusive instruction pairs, for example LDREX/STREX. ARM DDI 0403C Restricted... lock_acquire(unsigned *lockaddr) { if (*lockaddr ≡ 0) { // LDREX instruction instead of LDR CLREX... @ Is it already 0? (hence locked?) LDREX CMP ITT STREXNE @ @ @ @ @ @ @ If not...



Дата загрузки: 2016-12-29
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0.16/5
... "0x0001") t1 : Time of Execute LDREX instruction ~ Execute STREX instruction (Write... ~ Execute LDREX instruction again. t3 : Time of Read "0x0000" ~ Execute LDREX instruction again. t4 : Time of Execute LDREX instruction ~ Execute... t3 > t4 Execute LDREX instruction. 0x0001 Execute LDREX instruction. 0x0001 Execute STREX.... t2 Execute processing 1 processing 3. Execute LDREX instruction. Result of the execution... t3 has elapsed. 0x0000 Execute LDREX instruction. 0x0000 Judge the read... + 1".) Result is success. t3 Execute LDREX instruction. 0x0001 Execute STREX instruction... 6. Result of the execution Execute LDREX instruction. 0x0000 Execute STREX instruction...



Дата загрузки: 2017-01-23
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0.1/5
... DDI 0301D Assembler Load exclusive LDREX{cond} , [ ] Store exclusive STREX{cond... same data monitors as the LDREX and STREX instructions, a local and... same data monitors as the LDREX and STREX instructions, a local and... same data monitors as the LDREX and STREX instructions, a local and... instructions. 0x2, ARM1176JZF-S processors support: • LDREX and STREX • LDREXB, LDREXH, LDREXD... if U is set to 0 WSync LDREX, STREX, SWP, either access if... inter-process communication: • load-exclusive, LDREX, LDREXB, LDREXH, and LDREXD • store... non-shared memory regions, the LDREX{B,H,D} and STREX{B,H,D} instructions are presented... for any processor. 8.2.3 Example of LDREX and STREX usage This is..., or Either. Load exclusive instructions, LDREX, LDREXB, LDREXD, and LDREXH, trigger...,LDRB, LDRBT, LDRSB, LDRH, LDRSH, LDREX, LDREXB, LDREXH, LDREXD, STR, STRT... behavior for the SWP, SWPB, LDREX, and STREX instructions. In all..., , [Rn] 2 2 3 SWPB Rd, , [Rn] 2 2 3 LDREX , [Rn] 1 1 3 STREX, , , [Rn] 1 1 3 LDREX{B,H,D} , [Rn] 1 1 3 STREX{B,H,D} , , [Rn..., LDRSH, LDRH, LDRSB, LDRB, LDRBT, LDREX, RFE, STREX, SWP, and SWPB... memory synchronization. That is, the LDREX, STREX, SWP, and SWPB instructions...