Спутник ДЗЗ. Rising 2. [Редактировать]

SpriteSat это спутник дистанционного зондирования Земли который построен университетом Tohoku, Япония. Космический аппарат будет осуществлять съемку молний и порождаемых ими феноменами в верхних слоях атмосферы.

Дополнительные наименования

#НаименованияПоиск в новостяхПоиск в документах
1SpriteSatНайтиНайти
239769НайтиНайти

Дополнительная классификация

#Наименования
1Страна оператор(владелец) - Япония
2Страна производитель - Япония
3Тип оператора(владельца) - государственный
4Тип орбиты - НОО
5Все спутники ДЗЗ

Технические характеристики

#ХарактеристикаЗначение
1Масса, кг50
2Разрешение, метра5

Пусковые характеристики

#ХарактеристикаЗначение
1Код NSSDC2014-029D

Информация об удачном запуске

#ХарактеристикаЗначение
1Космодром Танегасима
2Дата пуска2014-05-24 at 03:05:00 UTC
3Полезная нагрузка 1xALOS 2
4Полезная нагрузка 1xUniform 1
5Полезная нагрузка 1xSOCRATES
6Полезная нагрузка 1xRising 2
7Полезная нагрузка 1xSPROUT
8Ракета-носитель 1xH2A202

Найдено 1000 документов по запросу «Rising 2». [Перейти к поиску]


Дата загрузки: 2017-06-15
Скачать документ
Скачать текст
0.05/5
...) Delay time, output clock gpmc_clk rising edge to D(4) – 2.2 D(4) + 1.2 D(4) – 2.2 D(4) + 1.2 output lower byte... – 2) is a multiple of 3) For OE rising edge (OE deactivated): – Case GpmcFCLKDivider... – 2) is a multiple of 3) For WE rising edge (WE deactivated): – Case GpmcFCLKDivider... after input pixel clock cam_pclk rising edge 1.82 3.25 ns (2) (2) (1) Related... after input pixel clock cam_pclk rising edge 1.82 3.25 ns (2) (2) (1) Related... after input pixel clock cam_pclk rising edge 1.08 2.27 ns (2) (2) (1) Related... after input pixel clock cam_pclk rising edge 1.82 3.25 ns (2) (2) (1) Related... 4.3.4, Processor Clocks. 6.6.1.1.1 Rising Edge as Activation Mode 6.6.1.1.1.1 Timing with Rising Edge as..., 2, and 3 (Sets #2 and #3) Timing Requirements—Rising Edge and Receive Mode(1) (2) NO..., 2, and 3 (Sets #2 and #3) Switching Characteristics—Rising Edge and Receive Mode(1) (2) NO... 6-49. McBSP4 (Set #1) Timing Requirements—Rising Edge and Receive Mode(1) (2) NO... 6-50. McBSP4 (Set #1) Switching Characteristics—Rising Edge and Receive Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Timing Requirements—Rising Edge and Receive Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Switching Characteristics—Rising Edge and Receive Mode(1) (2) NO... number: 1, 2, 3, 4, or 5. Figure 6-36. McBSP Rising Edge Receive Timing in Master.... McBSP Rising Edge Receive Timing in Slave Mode 6.6.1.1.1.2 Timing with Rising Edge..., 2, and 3 (Sets #2 and #3) Timing Requirements—Rising Edge and Transmit Mode(1) (2) NO..., 2, and 3 (Sets #2 and #3) Switching Characteristics—Rising Edge and Transmit Mode(1) (2) NO... 6-55. McBSP4 (Set #1) Timing Requirements—Rising Edge and Transmit Mode(1) (2) NO... 6-56. McBSP4 (Set #1) Switching Characteristics—Rising Edge and Transmit Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Timing Requirements—Rising Edge and Transmit Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Switching Characteristics—Rising Edge and Transmit Mode(1) (2) NO... number: 1, 2, 3, 4, or 5. Figure 6-38. McBSP Rising Edge Transmit Timing in Master... number: 1, 2, 3, 4, or 5. Figure 6-39. McBSP Rising Edge Transmit Timing in Slave... time, hsusb0_data[0:7] valid before hsusb0_clk rising edge 6.68 ns HSU6 th... time, hsusb0_data[0:7] valid after hsusb0_clk rising edge 0 ns HSU3 HSU4 (1) Related...[7:0] valid before output clock hsusbx_clk rising edge 9.3 ns Timing Requirements and...[7:0] valid after output clock hsusbx_clk rising edge ns (1) In hsusbx, x is...) Delay time, output clock hsusbx_clk rising edge to output data hsusbx_data...) Delay time, output clock hsusbx_clk rising edge to output data hsusbx_data... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26 ns HSSD8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC1 Interface... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26 ns HSSD8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns (1) In mmc1_dat...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition... time, mmc1_dat[n:0](3) valid before mmc1_clk rising clock edge 3.3 21.9 ns SD8... time, mmc1_dat[n:0](3) valid before mmc1_clk rising clock edge 3.3 21.9 ns SD8...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 13.6 55.1 ns... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 7.7 7.5 ns MMC1 Interface... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 13.6 55.1 ns... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 7.7 7.5 ns (1) In mmc1_dat...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](4) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](4) transition... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26.0 ns MMC8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC1 Interface... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26.0 ns MMC8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns (1) In mmc1_dat...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](5) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](5) transition... time, mmcx_dat[n:0](1) valid before mmcx_clk rising clock edge 3.4 23.8 ns HSSD8... time, mmcx_dat[n:0](1) valid after mmcx_clk rising clock edge 1.7 1.3 ns (1) In mmcx_dat...(clkL-doV) Delay time, mmcx_clk rising clock edge to mmcx_dat[n:0](2) transition... time, mmcx_dat[n:0](1) valid before mmcx_clk rising clock edge 3.3 21.9 ns SD8...(CLKOH-DATx) Delay time, mmcx_clk rising clock edge to mmcx_dat[n:0](6) transition...[n:0] valid after output clock mmcx_clk rising edge 1.3 0.9 ns (1) In mmx_dat[n:0], x is..., mmcx_clk rising clock edge to mmcx_cmd transition tR(do) Rising time, output... rising clock edge to mmcx_daty transition 37.2 ns tR(do) Rising time...



Дата загрузки: 2017-09-24
Скачать документ
Скачать текст
0/5
...(CLKH-nBEIV) Delay time, gpmc_clk rising edge to gpmc_nbe0_cle, gpmc_nbe1 invalid...(CLKH-nADV) Delay time, gpmc_clk rising edge to gpmc_nadv_ale transition G(7) – 1.9 G(7) + 4.1 G(7) – 2.1 G(7) + 4.1 G(7) – 2.6 G(7) + 4.9 ns...(CLKH-nADVIV) Delay time, gpmc_clk rising edge to gpmc_nadv_ale invalid D(4) – 1.9 D(4) + 4.1 D(4) – 2.1 D(4) + 4.1 D(4) – 2.6 D(4) + 4.9 ns...(CLKH-nOE) Delay time, gpmc_clk rising edge to gpmc_noe transition H(8) – 2.1 H(8) + 2.1 H(8) – 2.1 H(8) + 2.1 H(8) – 2.6 H(8) + 4.9 ns...(CLKH-nOEIV) Delay time, gpcm rising edge to gpmc_noe invalid E(5) – 2.1 E(5) + 2.1 E(5) – 2.1 E(5) + 2.1 E(5) – 2.6 E(5) + 4.9 ns...(CLKH-nWE) Delay time, gpmc_clk rising edge to gpmc_nwe transition I(9) – 1.9 I(9) + 4.1 I(9) – 2.1 I(9) + 4.1 I(9) – 2.6 I(9) + 4.9 ns...(CLKH-nBE) Delay time, gpmc_clk rising edge to gpmc_nbex_cle transition J(10...) – 2.1 M(17) + 4.1 M(17) – 2.1 M(17) + 4.1 M(17) – 2.6 M(17) + 4.9 rising edge to gpmc_io_dir low (OUT... – 2) is a multiple of 3) For OE rising edge (OE deactivated): – GpmcFCLKDivider = 0: – H = 0.5 * OEExtraDelay... – 2) is a multiple of 3) For WE rising edge (WE deactivated): – Case GpmcFCLKDivider... time, cam_wen valid after cam_pclk rising edge 1.08 2.27 ns (1) (2) (3) (4) , cam_pclk... time, cam_fld valid after cam_pclk rising edge 1.82 3.25 ns (1) (2) (3) (4) , cam_pclk... time, cam_fld valid after cam_pclk rising edge 1.08 2.27 ns (1) (2) (3) (4) 0.5*P 0.5*P ns... time, cam_d[9:0] valid after cam_pclk rising edge 1.82 3.25 ns (1) (2) (3) (4) 0.5*P 0.5*P The... characteristics are described for both rising and falling activation edges. McBSP1... number: 1, 2, 3, 4, or 5. 6.6.1.1.1 Receive Timing with Rising Edge as Activation Edge Table..., 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Receive Mode (1) NO..., 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Receive Mode (1) NO... 6-46. McBSP4 (Set #1) Timing Requirements – Rising Edge and Receive Mode (1) NO... 6-47. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Receive Mode (1) NO... (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Receive Mode (1) NO... (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Receive Mode (1) NO....ti.com 6.6.1.1.2 Transmit Timing with Rising Edge as Activation Edge Table..., 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Transmit Mode (1) NO..., 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Transmit Mode (1) NO... 6-52. McBSP4 (Set #1) Timing Requirements – Rising Edge and Transmit Mode (1) NO... 6-53. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Transmit Mode (1) NO... (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Transmit Mode (1) NO... (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Transmit Mode (continued... 3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Transmit Mode (1) NO... Mode(1)(2) (1) The active clock edge (rising or falling) on which mcspi_somi... Mode(1)(2)(3) (1) The active clock edge (rising or falling) on which mcspix_simo... time, hsusb0_data[0:7] valid before hsusb0_clk rising edge 6.7 ns HSU6 th(CLKH... time, hsusb0_data[0:7] valid after hsusb0_clk rising edge 0.0 ns HSU0 HSU3 HSU4... output hsusb0_data[0:7] invalid tr(do) Rising time, output signals 2.0 ns tf... time, hsusbx_data[0:7] valid before hsusbx_clk rising edge 9.3 ns HSU6 th(CLKH... time, hsusbx_data[0:7] valid after hsusbx_clk rising edge 0.2 ns HSU4 (1) In hsusbx... time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge 6 ns HSU3 ts(CLKH... time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge 0 ns HSU4 ts(DATAV... time, hsusbx_tll_data[7:0] valid before hsusbx_tll_clk rising edge 6 ns HSU5 th(CLKH... time, hsusbx_tll_data[7:0] valid after hsusbx_tll_clk rising edge 0 ns (1) In hsusbx, x is... time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge 6 ns HSU3 ts(CLKH... time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge 0 ns HSU4 ts(DATAV... time, hsusbx_tll_data[3:0] valid before hsusbx_tll_clk rising edge 3 ns (1) In hsusbx, x is... time, hsusbx_tll_data[3:0] valid after hsusbx_tll_clk rising edge MAX –0.8 ns Table 6-106... time, mmc1_datx valid after mmc1_clk rising clock edge 2.3 1.9 ns (1) (2) (3) (4) 236 Timing... time, mmc1_datx valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC3 tsu... time, mmc2_datx valid after mmc2_clk rising clock edge 2.3 1.9 ns MMC3 tsu...-DATx) 1.15 V Delay time, mmc1_clk rising clock edge to mmc1_datx transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition...(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx transition...(CLKOH-DATx) Delay time, mmc3_clk rising clock edge to mmc3_datx transition... time, mmc3_datx valid after mmc3_clk rising clock edge 8.9 8.9 ns (1) (2) Timing parameters...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition...(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx transition... time, mmc3_datx valid after mmc3_clk rising clock edge 2.3 1.9 ns (1) (2) (3) Timing Parameters...



Дата загрузки: 2017-09-24
Скачать документ
Скачать текст
0/5
...) Delay time, output clock gpmc_clk rising edge to D(4) – 2.2 D(4) + 1.2 D(4) – 2.2 D(4) + 1.2 output lower byte... – 2) is a multiple of 3) For OE rising edge (OE deactivated): – Case GpmcFCLKDivider... – 2) is a multiple of 3) For WE rising edge (WE deactivated): – Case GpmcFCLKDivider... after input pixel clock cam_pclk rising edge 1.82 3.25 ns (2) (2) (1) Related... after input pixel clock cam_pclk rising edge 1.82 3.25 ns (2) (2) (1) Related... after input pixel clock cam_pclk rising edge 1.08 2.27 ns (2) (2) (1) Related... after input pixel clock cam_pclk rising edge 1.82 3.25 ns (2) (2) (1) Related... 4.3.4, Processor Clocks. 6.6.1.1.1 Rising Edge as Activation Mode 6.6.1.1.1.1 Timing with Rising Edge as..., 2, and 3 (Sets #2 and #3) Timing Requirements—Rising Edge and Receive Mode(1) (2) NO..., 2, and 3 (Sets #2 and #3) Switching Characteristics—Rising Edge and Receive Mode(1) (2) NO... 6-49. McBSP4 (Set #1) Timing Requirements—Rising Edge and Receive Mode(1) (2) NO... 6-50. McBSP4 (Set #1) Switching Characteristics—Rising Edge and Receive Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Timing Requirements—Rising Edge and Receive Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Switching Characteristics—Rising Edge and Receive Mode(1) (2) NO... number: 1, 2, 3, 4, or 5. Figure 6-36. McBSP Rising Edge Receive Timing in Master.... McBSP Rising Edge Receive Timing in Slave Mode 6.6.1.1.1.2 Timing with Rising Edge..., 2, and 3 (Sets #2 and #3) Timing Requirements—Rising Edge and Transmit Mode(1) (2) NO..., 2, and 3 (Sets #2 and #3) Switching Characteristics—Rising Edge and Transmit Mode(1) (2) NO... 6-55. McBSP4 (Set #1) Timing Requirements—Rising Edge and Transmit Mode(1) (2) NO... 6-56. McBSP4 (Set #1) Switching Characteristics—Rising Edge and Transmit Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Timing Requirements—Rising Edge and Transmit Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Switching Characteristics—Rising Edge and Transmit Mode(1) (2) NO... number: 1, 2, 3, 4, or 5. Figure 6-38. McBSP Rising Edge Transmit Timing in Master... number: 1, 2, 3, 4, or 5. Figure 6-39. McBSP Rising Edge Transmit Timing in Slave... time, hsusb0_data[0:7] valid before hsusb0_clk rising edge 6.68 ns HSU6 th... time, hsusb0_data[0:7] valid after hsusb0_clk rising edge 0 ns HSU3 HSU4 (1) Related...[7:0] valid before output clock hsusbx_clk rising edge 9.3 ns Copyright © 2010–2011...[7:0] valid after output clock hsusbx_clk rising edge ns (1) In hsusbx, x is...) Delay time, output clock hsusbx_clk rising edge to output data hsusbx_data...) Delay time, output clock hsusbx_clk rising edge to output data hsusbx_data... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26 ns HSSD8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC1 Interface... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26 ns HSSD8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns (1) In mmc1_dat...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition... time, mmc1_dat[n:0](3) valid before mmc1_clk rising clock edge 3.3 21.9 ns SD8... time, mmc1_dat[n:0](3) valid before mmc1_clk rising clock edge 3.3 21.9 ns SD8...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 13.6 55.1 ns... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 7.7 7.5 ns MMC1 Interface... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 13.6 55.1 ns... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 7.7 7.5 ns (1) In mmc1_dat...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](4) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](4) transition... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26.0 ns MMC8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC1 Interface... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26.0 ns MMC8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns (1) In mmc1_dat...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](5) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](5) transition... time, mmcx_dat[n:0](1) valid before mmcx_clk rising clock edge 3.4 23.8 ns HSSD8... time, mmcx_dat[n:0](1) valid after mmcx_clk rising clock edge 1.7 1.3 ns (1) In mmcx_dat...(clkL-doV) Delay time, mmcx_clk rising clock edge to mmcx_dat[n:0](2) transition... time, mmcx_dat[n:0](1) valid before mmcx_clk rising clock edge 3.3 21.9 ns SD8...(CLKOH-DATx) Delay time, mmcx_clk rising clock edge to mmcx_dat[n:0](6) transition...[n:0] valid after output clock mmcx_clk rising edge 1.3 0.9 ns (1) In mmx_dat[n:0], x is..., mmcx_clk rising clock edge to mmcx_cmd transition tR(do) Rising time, output... rising clock edge to mmcx_daty transition 37.2 ns tR(do) Rising time...



Дата загрузки: 2017-09-24
Скачать документ
Скачать текст
0/5
... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge..., 0x2 = Falling edge triggered, 0x3 = Rising edge triggered, 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge..., 0x2 = Falling edge triggered, 0x3 = Rising edge triggered, 0x4 = Both edge..., 0x2 = Falling edge triggered, 0x3 = Rising edge triggered, 0x4 = Both edge..., 0x2 = Falling edge triggered, 0x3 = Rising edge triggered, 0x4 = Both edge..., 0x2 = Falling edge triggered, 0x3 = Rising edge triggered, 0x4 = Both edge..., 0x2 = Falling edge triggered, 0x3 = Rising edge triggered, 0x4 = Both edge... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x0 4-204 Preliminary... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x0 4-206 Preliminary... 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x0 4-210 Preliminary... RnB transition detection configuration. 0 = Detect rising edge 1 = Detect falling edge 0 RW... - INT_R_EN [1] RW KEYPAD input port rising edge (key-released) interrupt 0 = Disables...:4] – Reserved R KEYPAD input "release" interrupt (rising edge) status (read) and clear... "1" 1'b0 R KEYPAD input "release" interrupt (rising edge) status (read) and clear...



Дата загрузки: 2017-09-24
Скачать документ
Скачать текст
0/5
...) Delay time, output clock gpmc_clk rising edge to D(4) – 2.2 D(4) + 1.2 D(4) – 2.2 D(4) + 1.2 output lower byte... – 2) is a multiple of 3) For OE rising edge (OE deactivated): – Case GpmcFCLKDivider... – 2) is a multiple of 3) For WE rising edge (WE deactivated): – Case GpmcFCLKDivider... after input pixel clock cam_pclk rising edge 1.82 3.25 ns (2) (2) (1) Related... after input pixel clock cam_pclk rising edge 1.82 3.25 ns (2) (2) (1) Related... after input pixel clock cam_pclk rising edge 1.08 2.27 ns (2) (2) (1) Related... after input pixel clock cam_pclk rising edge 1.82 3.25 ns (2) (2) (1) Related... 4.3.4, Processor Clocks. 6.6.1.1.1 Rising Edge as Activation Mode 6.6.1.1.1.1 Timing with Rising Edge as..., 2, and 3 (Sets #2 and #3) Timing Requirements—Rising Edge and Receive Mode(1) (2) NO..., 2, and 3 (Sets #2 and #3) Switching Characteristics—Rising Edge and Receive Mode(1) (2) NO... 6-49. McBSP4 (Set #1) Timing Requirements—Rising Edge and Receive Mode(1) (2) NO... 6-50. McBSP4 (Set #1) Switching Characteristics—Rising Edge and Receive Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Timing Requirements—Rising Edge and Receive Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Switching Characteristics—Rising Edge and Receive Mode(1) (2) NO... number: 1, 2, 3, 4, or 5. Figure 6-36. McBSP Rising Edge Receive Timing in Master.... McBSP Rising Edge Receive Timing in Slave Mode 6.6.1.1.1.2 Timing with Rising Edge..., 2, and 3 (Sets #2 and #3) Timing Requirements—Rising Edge and Transmit Mode(1) (2) NO..., 2, and 3 (Sets #2 and #3) Switching Characteristics—Rising Edge and Transmit Mode(1) (2) NO... 6-55. McBSP4 (Set #1) Timing Requirements—Rising Edge and Transmit Mode(1) (2) NO... 6-56. McBSP4 (Set #1) Switching Characteristics—Rising Edge and Transmit Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Timing Requirements—Rising Edge and Transmit Mode(1) (2) NO... (Set #1), 4 (Set #2), and 5 Switching Characteristics—Rising Edge and Transmit Mode(1) (2) NO... number: 1, 2, 3, 4, or 5. Figure 6-38. McBSP Rising Edge Transmit Timing in Master... number: 1, 2, 3, 4, or 5. Figure 6-39. McBSP Rising Edge Transmit Timing in Slave... time, hsusb0_data[0:7] valid before hsusb0_clk rising edge 6.68 ns HSU6 th... time, hsusb0_data[0:7] valid after hsusb0_clk rising edge 0 ns HSU3 HSU4 (1) Related...[7:0] valid before output clock hsusbx_clk rising edge 9.3 ns Copyright © 2010–2011...[7:0] valid after output clock hsusbx_clk rising edge ns (1) In hsusbx, x is...) Delay time, output clock hsusbx_clk rising edge to output data hsusbx_data...) Delay time, output clock hsusbx_clk rising edge to output data hsusbx_data... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26 ns HSSD8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC1 Interface... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26 ns HSSD8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns (1) In mmc1_dat...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition... time, mmc1_dat[n:0](3) valid before mmc1_clk rising clock edge 3.3 21.9 ns SD8... time, mmc1_dat[n:0](3) valid before mmc1_clk rising clock edge 3.3 21.9 ns SD8...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](6) transition... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 13.6 55.1 ns... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 7.7 7.5 ns MMC1 Interface... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 13.6 55.1 ns... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 7.7 7.5 ns (1) In mmc1_dat...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](4) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](4) transition... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26.0 ns MMC8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC1 Interface... time, mmc1_dat[n:0](1) valid before mmc1_clk rising clock edge 5.6 26.0 ns MMC8... time, mmc1_dat[n:0](1) valid after mmc1_clk rising clock edge 2.3 1.9 ns (1) In mmc1_dat...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](5) transition...(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_dat[n:0](5) transition... time, mmcx_dat[n:0](1) valid before mmcx_clk rising clock edge 3.4 23.8 ns HSSD8... time, mmcx_dat[n:0](1) valid after mmcx_clk rising clock edge 1.7 1.3 ns (1) In mmcx_dat...(clkL-doV) Delay time, mmcx_clk rising clock edge to mmcx_dat[n:0](2) transition... time, mmcx_dat[n:0](1) valid before mmcx_clk rising clock edge 3.3 21.9 ns SD8...(CLKOH-DATx) Delay time, mmcx_clk rising clock edge to mmcx_dat[n:0](6) transition...[n:0] valid after output clock mmcx_clk rising edge 1.3 0.9 ns (1) In mmx_dat[n:0], x is..., mmcx_clk rising clock edge to mmcx_cmd transition tR(do) Rising time, output... rising clock edge to mmcx_daty transition 37.2 ns tR(do) Rising time...



Дата загрузки: 2017-06-15
Скачать документ
Скачать текст
0.07/5
... at the timer clock (TIMCLK) rising edge. Alternatively, writing to the... (1) Set the CLK_EN bit at rising of the peripheral clock (PCLK.... Counting is performed at the rising edge of the count clock... Ch.n-4/n-3 in I/O mode 8.  Select the rising edge as a trigger input edge... odd channel starts on the rising edge of output waveform (TOUT... TIOAn+1 pin n : Even  Select the rising edge as a trigger input edge...-based Simultaneous Startup Register (BTSSSR), a rising edge is input (ECK/TGIN... odd channel starts when the rising edge is detected in output... that for I/O mode 4.  Select the rising edge as a trigger input edge... to this mode.  Select the rising edge as a trigger input edge... using this register, select the rising edge as a trigger input edge... three external events (detection of a rising edge, a falling edge, or both... three external events (detection of a rising edge, a falling edge, or both... three external events (detection of a rising edge, a falling edge, or both... three external events (detection of a rising edge, a falling edge, or both... three external events (detection of a rising edge, a falling edge, or both... three external events (detection of a rising edge, a falling edge, or both... (↑ to ↓) / LOW pulse width (↓ to ↑) Rising cycle (↑ to ↑) / Falling cycle (↓ to... chart (when a restart is disabled) Rising edge detection The trigger is... chart (when a restart is enabled) Rising edge detection Restarted by the... chart (trigger restart is disabled) Rising edge detection The trigger is... chart (trigger restart is enabled) Rising edge detection Restarted by the... 0 0 0 0  0 0 0 1  /4 0 0 1 0  /16 0 0 1 1  /128 0 1 0 0  /256 0 1 0 1 External clock (rising edge event) 0 1 1 0 External clock (falling... bit8 Description 0 0 Trigger input disabled 0 1 Rising edge 1 0 Falling edge 1 1 Both edges... chart (when a restart is disabled) Rising edge detection THe trigger is... chart (when a restart is enabled) Rising edge detection Restarted by the... chart (trigger restart is disabled) Rising edge detection The trigger is... chart (trigger restart is enabled) Rising edge detection Restarted by the... 0 0 0 0  0 0 0 1  /4 0 0 1 0  /16 0 0 1 1  /128 0 1 0 0  /256 0 1 0 1 External clock (rising edge event) 0 1 1 0 External clock (falling... bit8 Description 0 0 Trigger input disabled 0 1 Rising edge 1 0 Falling edge 1 1 Both edges... a trigger input operation performed when a rising edge is specified as a valid... 0 0 0 0  0 0 0 1  /4 0 0 1 0  /16 0 0 1 1  /128 0 1 0 0  /256 0 1 0 1 External clock (rising edge event) 0 1 1 0 External clock (falling... disabled LOW level 0 1 External trigger (rising edge) HIGH level 1 0 External trigger... measurement ↑ to ↑ Cycle measurement between rising edges ↓ to ↓ Cycle measurement between... width measurement Cycle measurement between rising edges Cycle measurement between falling... (measurement) start: At detection of a rising edge Count (measurement) end: At... between rising edges is measured. Count (measurement) start: At detection of a rising edge Count (measurement) end: At detection of a rising edge W ↓ Count... (measurement) end: At detection of a rising edge In any measurement mode... measurement (↑ to ↓) 0 0 1 Cycle measurement between rising edges (↑ to ↑) 0 1 0 Cycle measurement between... Operation (In case of Signal Rising Edge Detection) Peak FRT count...) is ignored, irrespective of the rising or falling edge, and the... RT(0) rising edge Number of WFG timer counts from RT(1) rising edge... RTO(1) falling edge to RT(0) rising edge (Polarity is positive) Number... RTO(0) falling edge to RT(1) rising edge (Polarity is positive) The... ICU ch.(0). Handles only the rising edge of IC(0) signal input... ICU ch.(1). Handles only the rising edge of IC(1) signal input... the rising edge only, the falling edge only, or both rising and... performed upon detection of the rising edge of IC0 signal input... ICU ch.(0) was performed at a rising edge. Read Function [bit9] IEI1... ICU ch.(1) was performed at a rising edge. Read Function The following... multifunction timer EDGE=0 (Start at rising edge, and stop at falling... falling edge, and stop at rising edge) GATE signal of multifunction... stopped. Note: PPG startup at a rising edge or a falling edge of... edge  Detection of rising edge  Detection of both rising and falling edges...:PCM[1:0]="01") and AES[1:0]="10" (rising edge) and BES[1:0]="01" (falling... edge of BIN signal mean a rising edge, a falling edge, or both... Detection edge Level Check pin Rising edge Rising edge BIN AIN Falling... Down (3) Falling edge Low Up (4) Rising edge High Down (5) Low Up... Check pin Rising edge Rising edge BIN AIN Falling edge Rising edge AIN... counter counted up or down. A rising edge, a falling edge, or both... is counted up or down. A rising edge, a falling edge, or both.... Detects level "L". 1 0 Detects a rising edge. Detects level "H". 1 1 Detects a rising or falling edge.... 0 1 Detects a falling edge. 1 0 Detects a rising edge. 1 1 Detects rising and falling edges. [bit11.... 0 1 Detects a falling edge. 1 0 Detects a rising edge. 1 1 Detects rising and falling edges. MN709...



Дата загрузки: 2017-06-15
Скачать документ
Скачать текст
0.07/5
... Rising Edge Preset Falling Edge Reset Rising Edge Reset Falling Edge Capture Rising... a rising edge of the Preset Counter Bit of the corresponding Counter. A rising... rising edge of pulses applied to input A and decrements on the rising... Rising Edge 04(BCD) = Preset Falling Edge 05(BCD) = Reset Rising Edge 06(BCD) = Reset Falling Edge 07(BCD) = Capture Rising Edge... the Preset Value on a rising edge (Preset Rising Edge, Function 03) or... Rising Edge Load Counter with Preset Value Function 03: Preset Rising Edge... E(2('%<-@*4&'-,&*$'()*+ Section 3-4 the Preset Value at a rising edge of the Preset Counter... Counter to zero on a rising edge (Reset Rising Edge, Function 05) or... the Capture Register on a rising edge (Capture Rising Edge, Function 07) or... to zero on a rising edge (Capture-reset Rising Edge, Function 13) or... Input. \ Function 13: Capture-Reset Rising Edge Capture current Counter Value... 14 6 5 3 2 1 0 4 O3 O2 O1 O0 Rising edge Output (0-3) Corresponding Digital Output... = Preset Rising Edge 04 = Preset Falling Edge 05 = Reset Rising Edge 06 = Reset Falling Edge 07 = Capture Rising Edge 08... Continue (inverted) 13 = Capture-Reset Rising Edge 14 = Capture-Reset Falling... rising/falling edge* 0 (=O0) Offset Rising Offset + 1 Falling Offset + 2 Rising Offset + 3 Falling Offset + 4 Rising Offset + 5 Falling Offset + 6 Rising Offset + 7 Falling Offset + 8 Rising Offset + 9 Falling ~ ~ ~ 31 Offset + 62 Rising Offset... executed at the Outputs’ corresponding rising or falling edge. The application... 00 No Function Rising Edge 01 Gate Positive Rising Edge 02 Gate Negative Falling Edge 03 Preset Rising Edge Rising Edge 04 Preset Falling Edge Falling Edge 05 Reset Rising Edge Rising Edge 06 Reset Falling Edge Falling Edge 07 Capture Rising Edge Rising... Edge 13 Capture-Reset Rising Edge Rising Edge 14 Capture-Reset Falling... 15 Enable Reset Rising Edge 16 Disable Reset Rising Edge You can... of improperly sized objects 201902 I O R D (2 2 2 ) Rising edge D2 on Digital input... (too big: >= 5100 (=000013EC H)) 000100 M O V L (4 9 8 ) Rising edge of improperly sized objects... at rising/falling edge* 0 (=O0) Offset Rising Offset + 1 Falling 1 (=O1) Offset + 2 Rising Offset + 3 Falling 2 (=O2) Offset + 4 Rising Offset + 5 Falling 3 (=O3) Offset + 6 Rising Offset + 7 Falling Offset + 8 Rising Offset + 9 Falling Offset + 10 Rising Offset + 11 Falling Offset + 12 Rising Offset + 13 Falling Offset + 14 Rising Offset + 15 Falling Offset + 16 Rising Offset + 17 Falling Offset + 18 Rising Offset + 19 Falling 10 Offset + 20 Rising Offset + 21 Falling 11 Offset + 22 Rising Offset + 23 Falling 12 Offset + 24 Rising Offset + 25 Falling 13 Offset + 26 Rising Offset + 27 Falling 14 Offset + 28 Rising Offset + 29 Falling 15 Offset + 30 Rising Offset + 31... Interrupt executed at rising/falling edge* 16 Offset + 32 Rising Offset + 33... Rising Offset + 35 Falling Offset + 36 Rising Offset + 37 Falling Offset + 38 Rising Offset + 39 Falling Offset + 40 Rising Offset + 41 Falling Offset + 42 Rising Offset + 43 Falling Offset + 44 Rising Offset + 45 Falling Offset + 46 Rising Offset + 47 Falling Offset + 48 Rising Offset + 49 Falling Offset + 50 Rising Offset + 51 Falling Offset + 52 Rising Offset + 53 Falling Offset + 54 Rising Offset + 55 Falling Offset + 56 Rising Offset + 57 Falling Offset + 58 Rising Offset + 59 Falling Offset + 60 Rising Offset + 61 Falling Offset + 62 Rising...



Дата загрузки: 2017-06-15
Скачать документ
Скачать текст
0.09/5
RM0031 Reference manual STM8L05xx, STM8L15xx, STM8L162x, STM8AL31xx and STM8AL3Lxx microcontroller family Introduction This reference manual targets application developers. It provides complete information on how to use the STM8L05xx, STM8L15xx, STM8L16xx, STM8AL31xx and STM8AL3Lxx microcontroller memory and peripherals. The STM8L05xx/STM8L15xx/STM8L16xx/ STM8AL31xx/STM8AL3Lxx is a family of microcontrollers with different memory densities, packages and peripherals. These products are designed for ultralow power applications. Refer to the product datasheet for the complete list of available peripherals. For ordering information, pin description, mechanical and electrical device characteristics, please refer to the product datasheet. For information on the STM8 SWIM communication protocol and debug module, please refer to the user manual (UM0470). For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). For information on programming, erasing and protection of the internal Flash memory please refer to the STM8L Flash programming manual (PM0054). Table 1. Type Applicable products Part numbers Value line low density STM8L05xx devices: STM8L051x3 microcontrollers with 8-KB Flash Value line medium density STM8L05xx devices: STM8L052x6 microcontrollers with 32-KB Flash Value line high density STM8L05xx devices: STM8L052x8 microcontrollers with 64-KB Flash Low density STM8L15x devices: STM8L151C2/K2/G2/F2, STM8L151C3/K3/G3/F3 microcontrollers with 4-KB or 8-KB Flash Medium density STM8L15xx devices: STM8L151C4/K4/G4, STM8L151C6/K6/G6, STM8L152C4/K4 and STM8L152C6/K6 microcontrollers with 16-KB or 32-KB Flash Microcontrollers Medium density STM8AL31xx/STM8AL3Lxx devices: STM8AL3168, STM8AL3166, STM8AL3148,STM8AL3146, STM8AL3138, STM8AL3136, STM8AL3L68, STM8AL3L66, STM8AL3L48, STM8AL3L46 microcontrollers with 8-KB, 16-KB or 32-KB Flash Medium+ density STM8L15xx devices: STM8L151R6 and STM8L152R6 microcontrollers with 32-KB Flash (Wider range of peripherals than medium density devices) High density STM8L15xx devices: STM8L151x8 and the STM8L152x8 microcontrollers with 64-KB Flash (Same peripheral set as medium+) High density STM8L16xx devices: STM8L162x8 microcontrollers with 64-KB Flash (Same peripheral set as high density STM8L152 devices plus the AES hardware accelerator) October 2012 Doc ID 15226 Rev 10 1/575 www.st.com Contents RM0031 Contents 1 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.2 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 1.2.1 Description of CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.2.2 STM8 CPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Global configuration register (CFG_GCR) . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3.1 Activation level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3.2 SWIM disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.3.3 Description of global configuration register (CFG_GCR) . . . . . . . . . . . . 35 1.3.4 Global configuration register map and reset values . . . . . . . . . . . . . . . . 35 2 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3 Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . 37 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 Main Flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.5 3.6 3.4.1 Low density device memory organization . . . . . . . . . . . . . . . . . . . . . . . 39 3.4.2 Medium density device memory organization . . . . . . . . . . . . . . . . . . . . 40 3.4.3 Medium+ density device memory organization . . . . . . . . . . . . . . . . . . . 41 3.4.4 High density device memory organization . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.5 Proprietary code area (PCODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4.6 User boot area (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4.7 Data EEPROM (DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4.8 Main program area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4.9 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Memory...



Дата загрузки: 2017-06-16
Скачать документ
Скачать текст
0.05/5
RM0031 Reference manual STM8L15x and STM8L16x microcontroller family Introduction This reference manual targets application developers. It provides complete information on how to use the STM8L15x and STM8L16x microcontroller memory and peripherals. The STM8L15x/STM8L16x is a family of microcontrollers with different memory densities, packages and peripherals. ■ The medium density STM8L15x devices are the STM8L151Cx/Kx/Gx, STM8L152Cx/Kx microcontrollers with a 16-Kbyte or 32-Kbyte Flash memory density. Refer to the product datasheet for the complete list of available peripherals. ■ The medium+ density STM8L15x devices are the STM8L151R6 and STM8L152R6 microcontrollers with a 32-Kbyte Flash memory density. They offer a wider range of peripherals than the medium density devices. Refer to the product datasheet for the complete list of available peripherals. ■ The high density STM8L15x devices are the STM8L151x8 and STM8L152x8 microcontrollers with a Flash memory density equal to 64 Kbytes. They offer the same peripheral set as medium+ density devices. Refer to the product datasheet for the complete list of available peripherals. ■ The high density STM8L16x devices are the STM8L162x8 microcontrollers where the Flash memory density is equal to 64 Kbytes. They offer the same peripheral set as high density STM8L152 devices plus the AES hardware accelerator. Refer to the product datasheet for the complete list of available peripherals. They are designed for ultralow power applications. For ordering information, pin description, mechanical and electrical device characteristics, please refer to the product datasheet. For information on the STM8 SWIM communication protocol and debug module, please refer to the user manual (UM0470). For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). For information on programming, erasing and protection of the internal Flash memory please refer to the STM8L Flash programming manual (PM0054). September 2010 Doc ID 15226 Rev 6 1/577 www.st.com Contents RM0031 Contents 1 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.2 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 1.2.1 Description of CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.2.2 STM8 CPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Global configuration register (CFG_GCR) . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3.1 Activation level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3.2 SWIM disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.3.3 Description of global configuration register (CFG_GCR) . . . . . . . . . . . . 35 1.3.4 Global configuration register map and reset values . . . . . . . . . . . . . . . . 35 2 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3 Flash program memory and data EEPROM (Flash) . . . . . . . . . . . . . . . 37 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 Flash main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.5 3.6 2/577 3.4.1 Medium density device memory organization . . . . . . . . . . . . . . . . . . . . 39 3.4.2 Medium+ density device memory organization . . . . . . . . . . . . . . . . . . . 40 3.4.3 High density device memory organization . . . . . . . . . . . . . . . . . . . . . . . 41 3.4.4 Proprietary code area (PCODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.5 User boot area (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.6 Data EEPROM (DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.7 Main program area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5.2 Memory access security system (MASS) . . . . . . . . . . . . . . . . . . . . . . . 46 3.5.3 Enabling write access to option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Memory programming . . . . . . . . . . ....



Дата загрузки: 2017-09-24
Скачать документ
Скачать текст
0/5
... of geopolitical events coupled with rising U.S. inflation increased gold prices more... other currencies and their economies. A rising euro against the U.S. dollar, for...: falling dollar, falling interest rates, rising inflation, and investors seeking the.... These included plummeting world production, rising commercial demand by wealthier working... was somewhat stabilized by China’s rising production, where output rose 12... prices. Against the backdrop of rising oil prices and a falling U.S. dollar... combination of soaring inflation and rising unemployment was a vicious pattern that... dollar meant falling currencies and rising inflation. The second oil shock... on conventional theories indicating that rising or high interest rates boosted... the fourth quarter. To tackle rising inflation, the Federal Reserve raised... from a combination of accelerating growth, rising interest rates, and a temporary P1... ceiling throughout the year—despite rising from under 1.0 percent to 1.8 percent... pair trading volumes accelerated consistently, rising 42 percent to $501 billion... only 1.8 percent against EUR, while rising 15.8 percent and 8.7 percent against... stock indexes, gold, and oil. Rising commodities was another factor behind... taxes, surging war spending, and rising energy imports. EUR maintained its... greatest potential for appreciation and rising interest rates. As these flows... strong domestic demand fed into rising inflation, which reached 2.2 percent from... with rising food and agricultural raw materials, while gaining from a rising interest... ECB maintaining its preoccupation with rising inflation, markets anticipated more ECB... unemployment, higher interest rates, and rising inflation. An emerging drought pushed... in signaling its preoccupation with rising inflation, markets were beginning to... a robust growth foundation for the rising currency. Speculative interest also played... multidecade highs. The threat of rising inflationary pressures emerging from record... gauged via falling volatility and rising global equities—had triggered a nearly... of these three currencies during rising volatility and falling equities. The... in pharmaceutical stocks prompted by rising health care costs, expanding economic... higher-yielding currencies but also rising stocks, commodities, and even real..., a declining target currency, and/or a rising funding currency. In both cases... complacency arising from overconfidence with a rising market, or exuberance. Accordingly, the... to expose rising risk appetite, sometimes also known as rising complacency. Figure... with a phase of rising equities, characterized by rising bullishness and heightened investor... pay high interest rates. Conversely, rising risk appetite is correlated with... their confidence toward risk increased. Rising global growth and the corresponding... and JPY carry trades boosted rising equities. But subsequent market decline... find a fairly strong correlation between rising risk aversion and a strengthening in...-Iraq war nervousness, WMD speculation Rising U.S. inflation triggers rate fears... rate hike campaign to contain rising inflation. Nervousness about further Fed... their longermaturity holdings. And finally, rising short-term rates increase homeowners... boosted by a deteriorating trade deficit, rising domestic consumption, and negative savings... imbalance was increasingly translated into rising surpluses in developing countries. The... toward stressing the risks of rising inflation, while addressing the emerging... 4.9 percent respectively, primarily due to rising exports and falling imports, prompted... economic growth. During economic expansions, rising demand for industrial metals and... combination of cheap oil and rising investment spending fed into a powerful... balance of payments. Thus, while a rising budget deficit increases the financial... weighing on import demand via rising prices. Conversely, prolonged periods of... (Percent of Total Imports) 0 FIGURE 7.5 Rising share of U.S. oil imports as... to strengthening economic growth and rising inflationary pressures. Republicans have attributed... economic, regulatory, and diversification perspective. Rising commodity prices, improved political stability... suffering from slowing growth and rising unemployment was further stifled by... their currencies to a falling dollar. Rising inflation and falling oil receipts... rates) and the currency hit. Rising purchases of U.S. corporate stakes will... the past three recessions, namely rising inflation, surging oil prices, a deepening...’s decline, rising inflation, and increased jewelry purchases by the rising middle class... Zealand dollar benefited tremendously from rising prices of cheese and milk... cutting cycles being accompanied by rising yield spreads (positively sloping curves... central banks’ policy dilemmas between rising inflation and slowing economic growth... monetary policy largely toward combating rising energy prices. Reinstilling Confidence in.... Figure 9.4 shows the divergence between rising Fed funds rates and relatively...-keepcopper-shinning.html. Mitsuhito, Ono. “Rising Crude Oil Prices Affect the...