Samsung is reportedly taking a more cautious approach to the next generation of semiconductor lithography, delaying broader adoption of High-NA EUV technology until around 2030. The reported timeline places the technology closer to Samsung’s planned 1nm-class manufacturing rather than its immediate advanced-node production.

High-NA EUV is considered an important step in semiconductor manufacturing because it can create smaller patterns on silicon wafers than today’s conventional EUV systems. However, the equipment is significantly more expensive and currently offers lower throughput, making the timing of adoption an important economic decision for chipmakers.

Extreme ultraviolet lithography is already an important technology in advanced chip manufacturing. High-NA EUV takes the process further by increasing the numerical aperture from the approximately 0.33 used by current Low-NA EUV scanners to 0.55. The higher numerical aperture allows the lithography system to resolve finer patterns.

This could become increasingly important as manufacturers move towards increasingly smaller process nodes. However, High-NA EUV does not simply replace existing EUV machines across an entire chip. The technology can be used selectively on the most critical layers where extremely fine patterns are required, while less demanding layers can continue to use existing lithography systems.

The main issue surrounding High-NA EUV is not simply whether the technology works, but when it makes economic sense to use it in high-volume production. High-NA EUV machines are substantially more expensive than existing EUV equipment and have faced throughput challenges. Earlier reporting has placed the cost of a High-NA EUV system at roughly $400 million, compared with around $150 million for previous-generation EUV equipment. 

For semiconductor manufacturers, the cost of the scanner is only part of the equation. The investment has to be justified through wafer output, yield, process simplification, and the reduction of additional patterning steps. This helps explain why Samsung is reportedly looking towards the 1nm era around 2030 instead of immediately switching its manufacturing roadmap to High-NA EUV.

Samsung’s reported delay does not mean the company is stepping away from EUV lithography. Existing Low-NA EUV systems can continue to be used for advanced nodes, with manufacturers relying on techniques such as multi-patterning where necessary to produce increasingly fine structures.

That approach can be less expensive than immediately moving every relevant layer to High-NA EUV. The trade-off is additional manufacturing complexity, since multi-patterning can require more process steps and can affect production time and cost. The industry is therefore balancing the expense of purchasing High-NA equipment against the additional complexity involved in continuing to use existing systems.

The reported 2030 timeline is significant because High-NA EUV has long been associated with the industry’s move towards 1nm-class and sub-2nm manufacturing. At these advanced nodes, chipmakers face increasing difficulties in producing smaller structures with existing lithography techniques. High-NA EUV could eventually reduce some of the multi-patterning requirements by allowing finer features to be printed more directly.

However, the exact timing is not universal across the industry. Earlier industry analysis has suggested that the economic benefits of High-NA EUV will become more compelling around 1nm processes, expected around 2030, although there has been no single industry-wide date for adoption. 

Samsung’s cautious approach contrasts with Intel’s earlier push into High-NA EUV. Intel has already installed ASML’s High-NA EUV equipment at its Oregon research and development facility and has been developing the technology for future advanced manufacturing. Intel’s roadmap has therefore placed it among the industry’s earliest adopters.

The difference illustrates that chipmakers do not have identical reasons for adopting the technology. Intel’s process roadmap and its efforts to compete in advanced foundry manufacturing have encouraged earlier investment, while Samsung’s approach is more closely tied to the economics and requirements of its future process nodes.

For Samsung, waiting until the 1nm generation could allow High-NA EUV technology to mature before it becomes more important in volume manufacturing. The company can meanwhile continue extracting performance from existing EUV equipment through process improvements and patterning techniques.

For the wider semiconductor industry, Samsung’s reported timeline also highlights a broader issue: the most advanced manufacturing technology is not automatically the most economical technology to deploy immediately. High-NA EUV is designed to address the increasing difficulty of scaling semiconductor structures, but its cost, throughput, and supporting process requirements remain important factors in determining when manufacturers move from development to large-scale production.

Samsung is reportedly looking towards around 2030 for broader High-NA EUV adoption alongside its 1nm-class manufacturing plans. The delay reflects the cost and production challenges surrounding the technology, while existing EUV systems remain useful for advanced chip manufacturing. As semiconductor nodes continue shrinking, High-NA EUV is likely to become increasingly important, but its adoption will depend on when the technology becomes economically practical for high-volume production.