Двигательная установка. BIT-3. [Редактировать]

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12017-08-02. Первый ускоритель на основе твердого иода прошел очередной этап разработки.
Компания Busek Co. Inc. (изготовитель двигательных установок) подтвердил, что ее изделие "BIT-3" прошло этап критического анализа дизайна и в первом квартале 2018 года компания планирует осуществить производство летного изделия. В качестве топлива установка будет использовать твердый йод. В дальнейшем, согласно данным производителя, система должна будет устанавливаться на аппараты типа кубсат. В качестве тестовых аппаратов планируется использовать университетские Lunar IceCube и LunaH-Map. работы по созданию этих спутников финансируются за счет средств НАСА и имеют массу около 14 кг. Целевой орбитой аппаратов выбрана лунная полярная орбита, а в качестве средства выведения РН серии СЛС. Тэги: BIT-3BUSEK CO., INC.

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0.09/5
... enable signals. Eight-bit, 16-bit, and 32-bit transfers are supported. DEVSEL... Write command. Eight-bit, 16-bit, and 32-bit transactions are supported. The... Read command. Eight-bit, 16-bit, and 32-bit read transfers are supported... Burst Alignment (BA) bit (CTRL0, bit 4). When this bit is set, if a burst... Processing Setting LAPPEN (CMD2, bit 2 or CSR3, bit 5) to a 1 modifies the way... the transmit FIFO. The RTRY_LCOL bit (CMD3, bit 16) can be programmed... overrides the Disable Receive Broadcast bit (DRCVBC bit Am79C976 in the MODE... Disable Receive Physical Address bit (DRCVPA, CSR15, bit 13). an indication that... Start of Frame at Time = 0 Bit 0 Bit 7 Bit 0 Bit 7 Increasing Time Most Significant Byte.... The VLAN frame size bit (VSIZE, CMD3, bit 20) determines the maximum... Link Status. If the FDLSE bit (bit 8) is set, a value of 1 will... Disable Port Manager (DISPM) bit (CMD3, bit 14) is cleared to 0. Auto... Manager (DISPM) bit (CMD3, bit 14) to 1. (The DISPM bit corresponds to the...-Negotiation Ability bit (R1, bit 3) is 0 or if the XPHYANE bit in the...) bit ■ Flow Control Command (FCCMD) bit ■ Fixed Length Pause (FIXP) bit ■ 16-bit PAUSE... ROMBASE and bit 0 of ROM_CFG corresponds to bit 0 of ROMBASE. If a bit in... to ROMBASE. Bit 0 of ROM_CFG controls bit 0 of ROMBASE. If bit 0 of ROM_CFG... bit 0 of ROMBASE. This bit is the address decode enable bit. When this bit... Auto Increment (LAAINC) bit (FLASH_ADDR, bit 31 or BCR29, bit 14) is set... pin by setting the PME_EN_OVR bit (CMD3, bit 4). This is typically set... either the PME_EN bit (PMCSR, bit 8) or the PME_EN_OVR bit (CMD3, bit 4) are set... setting the MPEN_SW bit (CMD7, bit 1) or the MPEN_EE bit (CMD3, bit 6). Alternatively, Magic... setting the MPPEN_SW bit (CMD7, bit 2) or the MPPEN_EE bit (CMD3, bit 8) and deasserting... bit (STAT0, bit 11), the MPINT bit (INT0, bit 13), and the PME_STATUS bit (PMCSR, bit... PMAT_DET bit (STAT0, bit 12) is set. This causes the PME_STATUS bit (PMCSR, bit... the PMAT_MODE bit (CMD7,bit 3).The RUN bit (CMD0, bit 0) and RX_SPND bit (CMD0, bit 3) must... Write Enable (APROMWE) bit (BCR2, bit 8). If this bit is cleared to 0, the... or by setting the STOP bit. Bit Name Description 15-10 RES... the Disable Prefetchability (PREFETCH_DIS) bit (CMD3, bit 30). PREFETCH_DIS is normally loaded.... Read/write accessible. Sticky bit. This bit is reset by POR. H_RESET.... Read/write accessible. Sticky bit. This bit is reset by POR. S_RESET.... Read/write accessible. Sticky bit. This bit is reset by POR. S_RESET... contents of the value bit. If a bit in the bit map is cleared.... This bit is an alias of CSR15, bit 3. 7 6 VAL0 APAD_XMT Value bit for... bit (CMD2, bit 8) and of the ADD_FCS bit in the transmit descriptor. This bit.... This bit is an alias of BCR32, bit 7. Interrupt Level. This bit allows... OR’ed with EMPPLBA bit (CSR116, bit 6). This bit is an alias of... of PME_EN bit. This bit is an alias of CSR116, bit 10. 3 RWU_DRIVER... enabled when either this bit or BCR45, bit 7 is set. 2 MPPEN_SW Magic... DM_ERROR bit, but it does not clear the DM_TEST_FAIL bit. This bit should... bit. When this bit is set to a 1 by the host, the PVALID bit (bit... High 0 1 From ECS Bit From ESK Bit From EDI Bit High 0 0 0 LED1 LED0... (DATAPERR, bit 8), master abort (RMABORT, bit 13), or target abort (RTABORT, bit 12) occurs. This bit is... as undefined. This bit is the write enable bit for bit [0] of the... bit in INT0. This bit is an alias of BCR32, bit 14. This bit... is 1 and the mask bit TINTM (CSR3, bit 9) is 0. CSR0: Am79C976 Controller... the STOP bit. This bit will reset if the DXSUFLO bit (CSR3, bit 6) is... of the DXMTFCS bit (CSR15, bit 3) and of the ADD_FCS bit in the... (DATAPERR, bit 8), master abort (RMABORT, bit 13), or target abort (RTABORT, bit 12... (DATAPERR, bit 8), master abort (RMABORT, bit 13), or target abort (RTABORT, bit 12... has. This bit is OR’ed with EMPPLBA bit (CSR116, bit 6). 2 MPINT 1 MPINTE... FASTSPNDE bit (CSR7, bit 15). Refer to the bit description of the FASTSPNDE bit... Am79C976 controller whenever the MIIPD bit (BCR32, bit 14) transitions from 0 to... = 0, will set TXON bit (CSR0 bit 4) if STRT (CSR0 bit 1) is asserted. Read... = 0, will set RXON bit (CSR0 bit 5) if STRT (CSR0 bit 1) is asserted. Read...-46: Reserved CSR48: Reserved Bit Name Description Bit Name Description 31-0 RES... CSR49: Chain Polling Interval Bit Name Description Bit Name Description 31-16... operations are ignored. 9/14/00 Bit Bit Bit VER CSR100: Bus Timeout Manufacturer... LOW or MPEN bit (CSR5, bit 2) gets set to 1. This bit is OR... S_RESET or setting the STOP bit. 1 Bit Name Description 31-0 RES Reserved...: Master Mode Write Active Bit Name Description Bit Name Description 31-16... the state of the DWIO bit (BCR18, bit 7). 7-0 9/14/00 SWSTYLE Software... on the MIIPD bit will set the MIIPDTINT bit (CSR7, bit 1). 219 P R E L I M I N A R Y MIIPD... is written and the PMAT_MODE bit (bit 7) is 1, Pattern Match logic is... is written and the PMAT_MODE bit (bit 7) is 1, Pattern Match logic is... is written and the PMAT_MODE bit (bit 7) is 1, Pattern Match logic is...



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0.08/5
... 6.1 6.2 6.3 Chapter 7 About the memory map .............................................................................. 4-2 Bit-banding ................................................................................................. 4-5 ROM memory table .................................................................................... 4-7 Exceptions... Status Register bit assignments .............................................. 2-6 Interrupt Program Status Register bit assignments .................................................. 2-7 Bit functions of... bit assignments ..................................................... 8-14 Interrupt Clear-Pending Registers bit assignments ................................................ 8-15 Active Bit Register bit assignments ........................................................................ 8-15 Interrupt Priority Registers 0-31 bit... bit assignments ......................... 8-22 System Control Register bit assignments ............................................................... 8-24 Configuration Control Register bit... ........................................................................................................... 9-3 MPU Type Register bit assignments ......................................................................... 9-4 MPU Control Register bit assignments ..................................................................... 9-6 MPU Region... 0-3 bit assignments .................................................. 11-24 DWT Mask Registers 0-3 bit assignments ............................................................ 11-24 Bit functions... formats ......................................................... 2-12 Processor memory map ............................................................................................ 4-2 Bit-band mapping ...................................................................................................... 4-6 Stack contents after... bit assignments ......................... 8-22 System Control Register bit assignments ............................................................... 8-24 Configuration Control Register bit... MPU Type Register bit assignments ........................................................................ 9-4 MPU Control Register bit assignments ..................................................................... 9-5 MPU Region... base Thumb-2 instructions, 16-bit and 32-bit, and excluding blocks for... base Thumb-2 instructions, 16-bit and 32-bit. • Harvard processor architecture enabling... bus matrix converts bit-band alias accesses into bit-band region accesses. It performs: • — bit field extract for bit-band loads — atomic read-modify-write for bit...-bit instructions. Table 1-1 lists the 16-bit Cortex-M3 instructions. Table 1-1 16-bit... register value, immediate 12-bit value, and C bit ADC{S}.W , , # Add register value...) Operation Assembler Clear bit field BFC.W , # , # Insert bit field from one register... RSB{S}.W , , {, } Subtract immediate 12-bit value and C bit from register value SBC... normal execution running 16-bit and 32-bit halfword aligned Thumb and...) instruction, and the Thumb state bit (T-bit). Interruptible-continuable instruction field Load... data types: • 32-bit words • 16-bit halfwords • 8-bit bytes. Note Memory systems... region of memory to a bit in a bit-band region of memory. The... region to a corresponding bit, or target bit, in the bit-band region. The... position of the target bit in the bit-band memory region. • Bit_word_addr... the targeted bit. • Bit_number is the bit position (0-7) of the targeted bit. Figure 4-2 on page 4-6 shows examples of bit... at 0x23FFFFE0 maps to bit [0] of the bit-band byte at 0x200FFFFF... at 0x23FFFFFC maps to bit [7] of the bit-band byte at 0x200FFFFF... at 0x22000000 maps to bit [0] of the bit-band byte at 0x20000000... at 0x2200001C maps to bit [7] of the bit-band byte at 0x20000000... on the targeted bit in the bit-band region. Bit [0] of the value... the targeted bit in the bit-band region. Writing a value with bit [0] set writes a 1 to the bit-band bit, and writing a value with bit [0] cleared writes a 0 to the bit-band bit... have no effect on the bit-band bit. Writing 0x01 has the... indicates that the targeted bit in the bit-band region is set... is, 4, 2 or 1 in bit locations [3:0]. If the bit is set then that... with more than one bit set, or setting a bit that is not... bit always reads zero [1] FtStopped This bit always reads zero [0] FlInProg This bit... is never present, this bit reads as zero. Bit [8] of this register... into accesses to the bit-band region. Bit-band writes take two... bit-band access has completed. For a description of bit-band accesses, see Bit.... For more information about bit-banding, see Bit-banding on page 4-5. • • ARM... request. MEMATTRS[1:0] Output Memory attributes. Bit 0 = Allocate, Bit 1 = shareable. HMASTERS[1:0] Output Indicates...



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0.33/5
... memoria de E/S Direcciones de bit @@@@ @@ Número de bit (00 a 15) Indica la... Operando Especificación de direcciones de bit Descripción Se especifican directamente los... de canal y de bit para especificar un bit (introducir bits de entrada... 0001 02 Número de bit (02) Número de bit (00 a 15) Indica... 23 bits desde el bit 00 al bit 22 contienen la mantisa.... Los 8 bits desde el bit 23 al bit 30 contienen el Exponente... (Binario) Valor = (–1) Signo x 1.[mantisa] x 2 Signo (bit 63) 3 Exponente 1: negativo o 0: positivo Los 52 bits desde el bit 00 al bit 51 contienen la mantisa... 11 bits desde el bit 52 al bit 62 contienen el Exponente... producirá su salida. (Bit de salida) 0000 00 (Bit de salida) 0000...(350) S N S: Canal fuente N: Número de Bit BIT TEST LD TSTN 351 TSTN... OFF. N S: Canal fuente N: Número de Bit BIT TEST AND TST 350 AND...ón Obligatorio N S: Canal fuente N: Número de Bit BIT TEST AND TSTN 351 AND...ón Obligatorio N S: Canal fuente N: Número de Bit BIT TEST OR TSTN 351 TSTN... ejecución) del procesamiento lógico al bit especificado. Salida Obligatorio Invierte el... procesamiento lógico y lo envía al bit especificado. Salida Obligatorio Funciona como... @RSET %RSET !RSET*1 B: Bit !@RSET*1 !%RSET*1 MULTIPLE BIT SET SETA @SETA 530... *1 !@RSTB N: Número de Bit RSTB(533) desactiva el bit especificado en el... SV 2 SV 1 SV 0 0 Bit 7 hasta Finalización Indicadores (D1) Bit 2 Bit 1 Bit 0 COUNTER CNT (BCD... el rango 0: Fuera del rang D Bit T+1 Rango 0 A Rango 0 B T+2 0 T+3 Rango 1 A Rango 1 B T+4 1 S D+15... Obligatorio D S: Origen D: Destino Estado del bit invertido. Canal de destino DOUBLE.... MOVB(082) Estado del bit invertido. D Transfiere el bit especificado. D+1 Salida Obligatorio... E/S de S Salida Obligatorio S: Fuente (canal o bit deseado) D: Destino (registro de índice... C: Bit de comienzo N: Longitud de datos de desplazamiento N 1 bit Desplaza un bit hacia la izquierda N 1 bit SHIFT N-BIT DATA RIGHT... datos de desplazamiento N 1 bit N 1 bit 94 Desplaza un bit hacia la derecha Salida... canal de resultado 16-BIT TO 32-BIT SIGNED BINARY SIGN @SIGN... a 4 bits C Busca el bit más a la izquierda (Dirección de bit más alto) Salida Obligatorio... (m) se escribe en R). Bit de la izquierda Bit de la derecha n=2 (Comenzar... izquierda Busca el bit más a la izquierda (Dirección de bit más alto) Decodificación de... bits del canal de destino. N Bit Bit 15 00 D S S+1 S: Primer canal fuente S+2 N: Número de Bit D: Canal de S+3 destino . . . S+15 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 . . . . . . . . . 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 Bit 15 D 0 LINE TO... COLM(064) S . . . 0 1 1 1 Bit 15 N S 0 Bit 00 . . . . . . D D+1 D+2 D+3 . . . D+15 . 0 1 1 1 Bi Bit 15 106 Bit 00 Convierte... de destino N: Número de Bit Salida Obligatorio Bit 00 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 . . . . . . . . . 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 Salida Obligatorio Secci.... Salida Obligatorio B: Bit STEP START SNXT 009 SNXT(009) B B: Bit 3-21 Instrucciones... B: Operando de 806 bit EXIT(806) sin un bit de operando sale... B WAIT 805 B: Operando de bit Si el bit de operando está en... NOT 805 B: Operando de bit Si el bit de operando está en...(810) NOT. Bit de Bit de ope- Bit de ope- Bit de rando ON...ón Condición de ejecución Transfiere el bit especificado. Salida Obligatorio Cuenta el... son anteriores a EV1) Bit de retención IOM A50012 Bit de retención de...ón de tarjeta de memoria 5-2-5 Sobrescribir Bit de inicio de sustitución Transferencia... 226 a 231. Dirección 226 bit 0 Nombre Bit de inhabilitación de refresco cíclico... Unidad de E/S especial 0 : : 231 bit 15 Bit de inhabilitación de refresco cíclico... número de unidad 0. Bit “a” Pone en ON el bit “a” si el refresco... instrucción para direccionar indirectamente el bit o el canal deseados. 3. Desplace o aumente... Fuerza la reconfiguración del bit especificado. MULTIPLE BIT SET/RESET Fuerza la... error. Bit 00: No se utiliza. Bit 01: No se utiliza. Bit 02: Error de paridad Bit 03: Error de trama Bit 04: Error de overrun Bit 05: Error de tiempo de espera Bit 06: No se utiliza. Bit... tiempo de espera Bit 04: Error de sobrecarga Bit 03: Error de... consola de programación 80 bit 15 Estado del bit de retención IOM... arrancar 6-6-2 Configuración Valor predeterminado 0: El bit de retención IOM se pone... de progradirección 83, bit 15) mación, dirección 84, bit 15) Iniciar sin...ón de prueba y depuración Bit de inicio de muestreo Bit de inicio de... standby de edición online Bit de salida OFF Bit de retención de... Sí No Sí No Sí Sí Sí No Sí Sí Sí (bit del área auxi- Sí (bit del área liar de... SET/ RSET Sí Sí Sí Sí Sí MULTIPLE BIT SET/RESET SETA/ RSTA Sí (bit de comienzo y número... B batería compartimento 2 instalación 2 Bit de retención IOM 316 Bit de salida OFF...



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0.36/5
... PERIPHERALS - SAR ADC • 12-Bit (C8051F020/1) • 10-Bit (C8051F022/3) • ± 1 LSB INL • Programmable...™ Compatible), SPI™, and 8-bit ADC Two 12-bit DACs - - Two Analog Comparators.............................................................................................................145 16.1.1. 16-Bit MOVX Example.......................................................................................145 16.1.2. 8-Bit MOVX Example.........................................................................................145... (on-chip) True 12-bit (C8051F020/1) or 10-bit (C8051F022/3) 100 ksps...-bit) Programmable Counter Array Digital Port I/O’s 12-bit 100ksps ADC Inputs 10-bit 100ksps ADC Inputs 8-bit 500ksps ADC... VREF DAC1 DAC1 (12-Bit) DAC0 DAC0 (12-Bit) UART0 UART1 C R O S S B A R SMBus... VREF DAC1 DAC1 (12-Bit) DAC0 DAC0 (12-Bit) UART0 UART1 C R O S S B A R SMBus... shutdown when this bit is logic 0. Figure 5.1. 12-Bit ADC0 Functional Block... shutdown when this bit is logic 0. Figure 6.1. 10-Bit ADC0 Functional Block... XCHD A, @Ri CLR C CLR bit SETB C SETB bit CPL C 104 2 2 3 1 1 1 1 1 1 1 Clock Cycles... Description CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel Complement direct bit AND direct bit to Carry AND complement of direct bit to...-0xFF). #data - 8-bit constant #data16 - 16-bit constant bit - Direct-accessed bit in Data RAM or SFR addr11 - 11-bit... bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the... bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit... Write/Erase Security Bits. (Bit 7 is MSB.) Bit Memory Block 7 6 5 4 3 2 1 0 0xE000 - 0xFDFD... address byte (Bits7-1: 7-bit slave address; Bit0: R/W direction bit), one or more... bit (R/W) occupies the least-significant bit position of the address. The direction bit...=1, CKPHA=1) MISO/MOSI MSB Bit 6 Bit 5 Bit 4 NSS 200 Rev. 1.4 Bit 3 Bit 2 Bit 1 Bit 0 C8051F020/1/2/3 19.4. SPI... transmitted. 0 0 0 0 1 1 1 1 Bits2-0: BC2-BC0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 BIT Transmitted Bit 0 (LSB) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (MSB) SPIFRS2-SPIFRS0: SPI0... D4 D5 D6 D7 STOP BIT BIT TIMES BIT SAMPLING The baud rate... first), a programmable ninth data bit, and a stop bit. Mode 2 supports multiprocessor communications... SPACE START BIT D0 D1 D2 D3 D4 BIT TIMES BIT SAMPLING 208... first), a programmable ninth data bit, and a stop bit. The baud rate is... 0. All Modes: The Transmit Collision bit (TXCOL0 bit in register SCON0) reads... TXCOL0 bit also functions as the SM20 bit when the SSTAT0 bit in... RXOVR0 bit also functions as the SM10 bit when the SSTAT0 bit in... FE0 bit also functions as the SM00 bit when the SSTAT0 bit in... 1: 8-Bit UART, Variable Baud Rate Mode 2: 9-Bit UART, Fixed Baud Rate Mode 3: 9-Bit... required. RB80: Ninth Receive Bit. The bit is assigned the logic level... D4 D5 D6 D7 STOP BIT BIT TIMES BIT SAMPLING The baud rate... first), a programmable ninth data bit, and a stop bit. Mode 2 supports multiprocessor communications... SPACE START BIT D0 D1 D2 D3 D4 BIT TIMES BIT SAMPLING 218... first), a programmable ninth data bit, and a stop bit. The baud rate is... 0. All Modes: The Transmit Collision bit (TXCOL1 bit in register SCON1) reads... TXCOL1 bit also functions as the SM21 bit when the SSTAT1 bit in... RXOVR1 bit also functions as the SM11 bit when the SSTAT1 bit in... FE1 bit also functions as the SM01 bit when the SSTAT1 bit in... 1: 8-Bit UART, Variable Baud Rate Mode 2: 9-Bit UART, Fixed Baud Rate Mode 3: 9-Bit... required. RB81: Ninth Receive Bit. The bit is assigned the logic level... Timer 1: 13-bit counter/timer 16-bit counter/timer 8-bit counter/timer with auto-reload Two 8-bit counter... 0: 13-bit counter/timer Mode 1: 16-bit counter/timer Mode 2: 8-bit counter/timer... 0: 13-bit counter/timer Mode 1: 16-bit counter/timer Mode 2: 8-bit counter/timer with auto-reload Mode 3: Two 8-bit... source. The Counter/Timer Select bit C/T2 bit (T2CON.1) selects the clock... source. The Counter/Timer Select bit C/T4 bit (T4CON.1) selects the clock... Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each is described... Output 1 X Frequency Output 1 X 8-Bit Pulse Width Modulator 1 X 16-Bit Pulse Width Modulator... Toggle x Enable PCA Timebase 256 8-bit Adder 8-bit Comparator PCA0L Rev. 1.4 match... clearing the ECOMn bit to ‘0’. Figure 23.8. PCA 8-Bit PWM Mode Diagram... Width Modulation Enable This bit selects 16-bit mode when Pulse Width... is enabled (PWMn = 1). 0: 8-bit PWM selected. 1: 16-bit PWM selected. ECOMn: Comparator.../1/2/3 Table 24.1. Boundary Data Register Bit Definitions Bit 118, 120, 122, 124.... This bit is placed ate bit 0 to allow polling by single-bit shifts...



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0.12/5
..., or G19 by setting bit 1 (parameterG18) and bit 2 (parameter G19) of parameter... the MDL bit (bit 0 of parameter 5431). (When the MDL bit is set... state specified in the G01 bit (bit 0 of parameter 3402). Limitations D Controlled... notation by using the DPI bit (bit 0 of parameter 3401).Values can... direction positioning (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... the setting at bit 4 (DOV) of parameter 5200, bit 3 (OVU) of parameter... or G60 (when the MDL bit (bit 0 of parameter 5431) is set... are selected using the PCP bit (bit 5) of parameter 5200. Format G84... retracted by distance d. The DOV bit (bit 4) of parameter 5200 specifies whether... performed to point R. The DOV bit (bit 4) of parameter 5200 specifies whether... F, the specification of the DOV bit (bit 4) of parameter 5200 is also... coordinate system in the DAK bit (bit 6 of parameter 3106). D Three–dimensional... linear interpolation positioning (the LRP bit (bit 1 of parameter 1401) is set... is executed. (Set the LRP bit, bit 1 of parameter No.1401, to... are performed) If the TAL bit (bit 3 of parameter No. 5001) is... s referenceposition=Intermediate position When CCN (bit 2 of parameter No.5003)=1 [FS15... referenceposition=Intermediate position When CCN (bit 2 of parameter No.5003)=1 [FS15... s Intermediateposition= Return position When CCN (bit 2 of parameter No.5003)=1 [FS15... program for when the RIN bit (bit 0 of parameter 5400) is set... the FS15. If the ABS bit (bit 3 of parameter 2409) is set... are used to read a signal bit by bit. Variable #1032 is used... are used to write a signal bit by bit. Variable #1132 is used... is performed on binary numbers bit by bit. Conversion from BCD to... indicated below: When the NAT bit (bit 0 of parameter 6004) is set... to 90_ When the NAT bit (bit 0 of parameter 6004) is set... as follows: When the NAT bit (bit 0 of parameter 6004) is set..., #1 is 225.0. When the NAT bit (bit 0 of parameter 6004) is set... O0001 ; : T23 ; : M30 ; O9000 ; : : : M99 ; Bit 5 of parameter 6001 = 1 Explanations D Call... PROGRAMMING B–63534EN/02 1. Set bit 2 (SBP) of bit type parameter No. 3404... (ROAx bit (bit 0 of parameter 1008) is set to 1). If the RAAx bit (bit... movement respectively. If the RAAx bit (bit 3 of parameter 1008) is set... 0, the setting by the RABx bit (bit 1 of parameter 1008) becomes significant... RAAx bit (bit 3 of parameter 1008) is set to 1, the RABx bit (bit 1 of... : +Z –Z C: Z: P: Compensation direction : (f) –C (d) +C – – + + C: Z: P: Compensation direction : – – – – 2 When bit 2 (HDR) of parameter No. 7700... : + +Z –C –Z C : – Z : – P : + Compensation direction : + C : – Z : – P : – Compensation direction : – 2 When bit 2 (HDR) of parameter No. 7700.... (e) +Z (d) +Z +C +Z –C –Z C Z P Cmp. direc. : : : : – – + + C Z P Cmp. direc. : : : : – – – – (2) When bit 2 (HDR) of parameter No.7700... : + –C C : –, Z : –, P : – Compensation direction : – When the HDR bit is set to 0 ((a), (b), (c), and (d) are... same as when the HDR bit is set to 1) (f) (e) +Z –Z –C C : –, Z : +, P : + Compensation direction... acceleration/ deceleration type. When bit 7(BDO) and bit 1(NBL) of parameter No... If “1” is set to bit 7(BDO) and bit 1(NBL) of parameter No...=2 (channel 2) I/O CHANNEL=3 (channel 3) 0102 Stop bit and other data Number specified...: (1) Positioning (G00): . . . . . . . . . . . . . . . . . . . . . (2) Linear interpolation (G01): . . . . . . . . . . . . . . . Bit 0 (JAXx) of (3) Automatic reference position... return (G30): . (5) M codes (miscellaneous functions): . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit 0 (JMF) of parameter No. 7002... No. 7002 (7) T codes (tool functions): . . . . . . . Bit 2 (JSF) of parameter No. 7002 (8) B codes (second auxiliary functions): . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit 3 (JBF) of parameter No. 7002... at address P. If the SBP bit (bit 2) of parameter No.3404 is....4 Parameter 0138 #7 DNM #6 #5 #4 #3 #2 #1 [Data type] Bit #7 (DNM) The DNC operation with... be disabled by setting bit 0 (WOF) and bit 1 (GOF) of parameter 3290... error compensation (setting the BDP bit (bit 0 of parameter 3605) to 1), specify... error compensation (setting the BDP bit (bit 0 of parameter 3605) to 1), specify... codcontrol (bit 5 of parameter No. 4001 and bit 4 of parame- er (bit 5 of... command. 20 Check bit 5 of parameter No. 4001, bit 5 of parameter No...



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0.11/5
... Considerations ............................................................... 776 18.3.15 Bit Time and Bit Rate ................................................................................................... 776 18.3.16... Complete Data Transfer with a 7-Bit Address ....................................................... 691 R/S Bit in First Byte ............................................................................................ 691... USEFRACT bit to the DIV400 bit and the FRACT bit to the SYSDIV2LSB bit..., SRCR1 , and SRCR2. bit A single bit in a register. bit field Two or more...-2 technology combines both 16-bit and 32-bit instructions to deliver the... and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization... ■ 16-bit general-purpose timer with an 8-bit prescaler ■ 32-bit Real-Time... and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization... data types: – 32-bit words – 16-bit halfwords – 8-bit bytes ■ Memory formats - The... register value, immediate 12-bit value, and C bit ADC{S}.W , , # Add register value... RSB{S}.W , , {, } Subtract immediate 12-bit value and C bit from register value SBC... with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes...:23] PWRDN2, bit[13] PWRDN, bit[13] BYPASS2, bit[11] BYPASS, bit[11] OSCSRC2... by using the formula: bit-band alias = bit-band base + (byte offset... DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit... of the device. The NW bit (bit 31) indicates that the register... address bit associated with the data bit is cleared, the data bit is... Bus supports the traditional 8-bit and 16-bit interfaces popularized by the... ■ 16-bit general-purpose timer with an 8-bit prescaler ■ 32-bit Real-Time... in 16-bit PWM or 32-bit RTC mode, this bit must be... in 16-bit PWM or 32-bit RTC mode, this bit must be... bit and the SYNCWAIT bit starts sampling once this bit is written. 0 This bit... is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part... the setting of the HSE bit (bit 5) in UARTCTL). This reference clock... the setting of the HSE bit (bit 5) in UARTCTL (described in “Transmit... bits Start bit UnTx 1 0 0 0 1 Stop bit 0 0 1 1 1 UnTx with IrDA 3 16 Bit period Bit period... not have a valid stop bit (a valid stop bit is 1). 0 No framing error... not have a valid stop bit (a valid stop bit is 1). 0 No framing error... clock after the last bit of the 8-bit control message has been... clock after the last bit of the 8-bit control message has been... 4-bit data 0x4 5-bit data 0x5 6-bit data 0x6 7-bit data 0x7 8-bit data 0x8 9-bit data 0x9 10-bit data 0xA 11-bit data 0xB 12-bit data 0xC 13-bit data 0xD 14-bit data 0xE 15-bit data 0xF 16-bit... last data bit (if the EOT bit is set). This bit is cleared... by an eighth bit, which is a data direction bit (R/S bit in the I2CMSA register). If the R/S bit is clear... BUSY bit=0? YES Read I2CMCS ERROR bit=0? NO NO NO BUSBSY bit=0? YES... I2CMCS NO YES NO BUSBSY bit=0? ERROR bit=0? NO YES Write ---01011... consists of one bit: the DA bit. The DA bit enables and disables... Compact Stereo mode size (16-bit or 8-bit), provide indication of whether...-Justified, Compact Stereo, 16-bit samples, 32-bit system data size). June... RMTEN bit to leave the TXRQST bit unchanged ■ Set the EOB bit for... is required to send a dominant bit (ACK bit, overload flag, or active...) Module unit of the bit time; the bit timing logic (configured by... the next data bit, handling a CRC bit, determining if bit stuffing is required... bit timing configuration starts with a required bit rate or bit time. The resulting bit time (1/bit rate) must... ns 400 ns = 2 × tq bit time = tSync + bit time = tSync + tPhase 1 + tPhase2... (40m) 220 ns 1 µs = 1 × tq bit time = tSync + bit time = tSync + tPhase 1 + tPhase2... was Low (logical 0). 0x5 Bit 0 Error A Bit 0 Error indicates that the device... used to program the bit width and bit quantum. Values are programmed... the RESUME bit and clear the SUSPEND bit. While the RESUME bit is... from FIFOs may be 8-bit, 16-bit or 32-bit as required, and... REQPKT bit is set. Setting this bit ensures that the DT bit is... be written (see DT bit). This bit is automatically cleared once the... be written (see DT bit). This bit is automatically cleared once the... be written (see DT bit). This bit is automatically cleared once the... Pin Default State GPIOAFSEL Bit GPIOPCTL PMCx Bit Field PA[1:0] UART0 1 0x1... port E bit 3. PE4 6 - I/O TTL GPIO port E bit 4. PE5 5 - I/O TTL GPIO port E bit 5. PE6 2 - I/O TTL GPIO port E bit 6. PE7 1 - I/O TTL GPIO port E bit 7. PF0...



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0.12/5
... Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value... CLOCK SOURCES Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 — — FCMEN IESO... REFERENCE CLOCK SOURCES Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 — — FCMEN IESO... REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN... OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE... WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE... ASSOCIATED WITH DATA EEPROM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page EECON1 EEPGD... OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 ANSA3... WITH PORTA Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 — — FCMEN IESO... ASSOCIATED WITH THE FVR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page FVREN FVRRDY... OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — CHS4... ASSOCIATED WITH THE DAC MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page FVRCON FVREN... REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 ANSA3... ASSOCIATED WITH SR LATCH MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 ANSA3... OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSB7 ANSB6... OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE... WITH DATA SIGNAL MODULATOR MODE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page MDCARH MDCHODIS... OF REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PxM1(1) PxM0(1) DCxB1 DCxB0 CCPxM3... OF REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PxM1(1) PxM0(1) DCxB1 DCxB0 CCPxM3... OF REGISTERS ASSOCIATED WITH PWM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page PxM1(1) PxM0... = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDOx (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDIx (SMP = 1) bit 0 bit 7 Input... reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 SDIx bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt... = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt... = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt...-3: REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE... REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL... Set-up bit 1 bit 7/8 Stop bit Start bit bit 0 Word 1 RCREG bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word... REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL... Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto... ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL... MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX... ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL... REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 122 ANSELA...



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0.16/5
... Concepts 2-1-4 Addressing I/O Memory Areas Bit Addresses @@@@ @@ Bit number (00 to 15) Indicates... 0001 02 0001 02 Bit number (02) Bit number (00 to 15... 2-1 Basic Concepts Data 16-bit constant 32-bit constant Operand Data form... The 23 bits from bit 00 to bit 22 contain the mantissa.... Exponent The 8 bits from bit 23 to bit 30 contain the exponent... The 52 bits from bit 00 to bit 51 contain the mantissa.... The 11 bits from bit 52 to bit 62 contain the exponent...-differentiated input instruction ■ Timing Chart Bit A Bit B Bit A Bit B Input-differentiated Instructions Upwardly Differentiated... Section 2-1 Basic Concepts ■ Timing Chart Bit A @SET Bit A Operation of SET • Input... OFF to ON. ■ Timing Chart Bit A Bit B Bit A Bit B 1 cycle • Input Instructions (Logical Starts... OFF to ON. ■ Timing Chart Bit A Bit B Bit A Bit B 1 cycle 37 Section 2-1 Basic Concepts... ON to OFF. ■ Timing Chart Bit A %SET Bit A Operation of SET • Input... after one cycle. ■ Timing Chart Bit A Bit B Bit A Bit B 1 cycle Note Unlike the upwardly... ON to OFF. ■ Timing Chart Bit A Bit B Bit A Bit B 1 cycle 2-1-9 I/O Instruction Timing The following... a logical start. Special Output bit Input bit instruction Connecting line Right bus... bit will be overwritten and not output. (Output bit) 0000 00 (Output bit) 0000 00 5. An input bit cannot be... N: Bit number BIT TEST LD TSTN 351 TSTN(351) S N S: Source word N: Bit number BIT TEST AND TST 350 AND TST(350) S N S: Source word N: Bit number BIT TEST AND TSTN 351 AND... rung Required N S: Source word N: Bit number BIT TEST OR TSTN 351 TSTN... @RSET %RSET !RSET*1 B: Bit !@RSET*1 !%RSET*1 MULTIPLE BIT SET SETA @SETA 530... 7 to SV 2 SV 1 SV 0 0 Bit 7 to Bit 2 Bit 1 Bit 0 COUNTER Count CNT input (BCD.... Output Required S S+1 Bit status inverted. D Transfers the specified bit. D+1 Output Required Section... bit N: Shift data length N−1 bit Shifts one bit to the left N−1 bit SHIFT N-BIT DATA... C: Beginning bit N: Shift data length N−1 bit Shifts one bit to the right N−1 bit 97... R: 1st result word 16-BIT TO 32-BIT SIGNED BINARY SIGN @SIGN... with second digit.) 4-to-16 bit decoding (Bit m of R is turned ON... with first byte.) 8-to-256 bit decoding (Bit m of R to R+15 is... word. 16-to-4 bit conversion C FInds leftmost bit (Highest bit address) S: 1st source...-4 bit decoding (Location of leftmost bit (m) is writ-ten to R.) Leftmost bit Rightmost bit n=2 (Start with digit 2.) R 256-to-8 bit conversion C l=0 (Convert... range.) Leftmost bit Finds leftmost bit (Highest bit address) 256-to-8 bit decoding (The location of the leftmost bit... source word N: Bit number D: Destination word N Bit 15 N S S+1 S+2 S+3 . . . S+15 Bit 00 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 . . . . . . . . . 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 Bit 15 D 0 LINE TO COLUMN COLM @COLM 064 COLM(064) S Bit...). Bit 15 D N S: Source word D: 1st destination word N: Bit number Output Required S 0 Bit 00 . . . . . . . 0 1 1 1 Bi Bit 15 D D+1 D+2 D+3 . . . D+15 Output Required Bit 00...-bit floating-point data) S R+1 Result (32-bit floating-point data) R Raises a 32-bit... the specified I/O words. I/O bit area or Special I/O Unit bit area St I/O Unit...) WAIT B WAIT 805 B: Bit operand If the operand bit is OFF (ON...) WAIT NOT 805 B: Bit operand If the operand bit is OFF (ON... B: Bit operand Operand bit ON Block program Required Operand Operand Operand bit OFF bit OFF bit OFF Loop repeated Note The status of the operand bit...: Disables the Replacement Start Bit (A65015). This bit is automatically turned OFF... Unit with unit number 0. Bit “a” Turns ON bit “a” if data refreshing fails...-sets the specified bit. Force-resets the specified bit. Force-sets, force.... Bit 00: Not used. Bit 01: Not used. Bit 02: Parity error Bit 03: Framing error Bit 04: Overrun error Bit 05: Timeout error Bit 06: Not used. Bit... the built-in input bit turns ON. 2. Output bit A turns ON in... address +80, bit 15 IOM Hold Bit 0: The IOM Hold Bit is cleared... Console address 84, bit 15) address 83, bit 15) To start without... Error Log Pointer Reset Bit FPD Teaching Bit A50014 A59800 Operation When... Online Edit Disable Bit (A52709). Online Edit Disable Bit A52709 Online Editing... this bit from the user program. Sampling Start Bit Trace Start Bit Trace... Yes No Yes (*1) No BIT TEST Yes (Bit position specified in binary...



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0.45/5
... bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IPSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 EPSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PRIMASK register bit definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FAULTMASK register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 BASEPRI register bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CONTROL register bit definitions... EPSR bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PSR bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PRIMASK bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FAULTMASK bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 BASEPRI bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CONTROL bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bit-band... only write to this bit. Reading the bit returns the reset value... high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3.... The bit assignments are: Table 4. APSR bit definitions Bits Description Bit 31 N: Negative... did not result in a borrow bit. Bit 28 V: Overflow flag: 0: Operation did... types: – 32-bit words – 16-bit halfwords – 8-bit bytes • supports 64-bit data transfer... bit-band regions. Bit-banding provides atomic operations to bit data, see Section 2.2.5: Bit... here. This region includes bit band and bit band alias areas, see... Device (1) This region includes bit band and bit XN (1) band alias areas... use of DMB instructions. 2.2.5 Bit-banding A bit-band region maps each word... a bit-band alias region to a single bit in the bit-band region. The bit... is also bit addressable through bit-band alias. 0x220000000x23FFFFFF SRAM bit-band alias... is also bit addressable through bit-band alias. 0x420000000x43FFFFFF Peripheral bit-band alias... position of the target bit in the bit-band memory region. • Bit_word_addr... the targeted bit. • Bit_number is the bit position, 0-7, of the targeted bit. Figure... at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x200FFFFF... at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF... at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000... at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000... region updates a single bit in the bit-band region. Bit[0] of the value... the targeted bit in the bit-band region. Writing a value with bit[0] set... bit, and writing a value with bit[0] set to 0 writes a 0 to the bit-band bit... tests the returned status bit. If this bit is: 0: The read-modify... updated to the last bit shifted out, bit[n-1], of the register Rm... updated to the last bit shifted out, bit[n-1], of the register Rm... is updated to the last bit rotation, bit[n-1], of the register Rm... bit 8 to bit 19 (12 bits) of R4 to 0 ; Replace bit 8 to bit 19 (12 bits) of R9 with ; bit 0 to bit 11..., #4 ; ; R8, R11, #9, #10 ; ; Extract bit 20 to bit 23 (4 bits) from R1... 8-bit value to a 32-bit value. H: Extends a 16-bit value to a 32-bit value... disabled, the processor ignores this bit. Bit 1 HFNMIENA: Enables the operation of... of interrupts to each register bit. A bit reads as 1 if the status...



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0.33/5
... diagram 2.4.3.1 Miscellaneous register Miscellaneous Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 $000C POR INTP INTN INTE... register EEPROM/ECLK control Address bit 7 bit 6 bit 5 bit 4 $0007 0 0 0 0 bit 3 bit 2 bit 1 bit 0 State on reset ECLK.... Address Options (OPTR)(1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 $0100 State on reset bit 1 bit 0 EE1P SEC Not...) $0001 Port C data (PORTC) $0002 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined... Rev. 4.1 3.8 Miscellaneous register Address Miscellaneous bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 $000C POR(1) INTP INTN INTE... feature. EEPROM/ECLK control Address bit 7 bit 6 bit 5 bit 4 $0007 0 0 0 0 bit 3 bit 2 bit 1 bit 0 State on reset ECLK... A and B (PORTA and PORTB) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Port A data... (PORTC) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 PC2/ ECLK $0002 bit 1 bit 0 State on reset Undefined Each bit can... D (PORTD) Port D data (PORTD) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset $0003 PD7... A/D status/control $0009 bit 7 bit 6 bit 5 COCO ADRC ADON bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0 CH3... Port A data direction (DDRA) bit 7 bit 6 bit 5 bit 4 bit 3 $0004 bit 2 bit 1 bit 0 State on reset 0000 0000... and alternate counter register Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Timer counter... low $0019 1111 1100 Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Alternate counter...). 5 Timer control (TCR) bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Address bit 7 bit 6 bit 5 $0012 ICIE OCIE... bit. Address bit 7 bit 6 bit 5 bit 4 bit 3 $0013 ICF1 OCF1 TOF ICF2 OCF2 Timer status (TSR) 5 bit 2 bit 1 bit.... 5.3.1 Input capture register 1 (ICR1) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Input capture... 5.6). 5.3.2 Input capture register 2 (ICR2) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Input capture.... 5.4.1 5 Output compare register 1 (OCR1) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Output compare.... 5.4.2 Output compare register 2 (OCR2) Address 5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Output compare...) MC68HC05B6 Rev. 4.1 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $000A Address Pulse length modulation B (PLMB) bit 7 State on reset 0000 0000 bit 7 bit 6 bit 5 bit 4 $000B PROGRAMMABLE TIMER bit 3 bit 2 bit 1 bit 0 State... (SCDR) Address SCI data (SCDR) 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0011 State on reset 0000... functions. SCI control (SCCR2) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset $000F TIE... it, PLMA and PLMB. Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Pulse length... D/A converters. 7.1 Miscellaneous register Miscellaneous Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 $000C POR INTP INTN INTE... (PORTD) Port D data (PORTD) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset $0003 PD7... (ADDATA) Address A/D data (ADDATA) bit 7 bit 6 bit 5 bit 4 bit 3 $0008 bit 2 bit 1 bit 0 State on reset 0000 0000.../control (ADSTAT) $0009 bit 7 bit 6 bit 5 COCO ADRC ADON bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0 CH3... Section 9.1.2). 9.1.2 Miscellaneous register Address Miscellaneous 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 $000C POR(1) INTP INTN INTE... MC68HC05B6 Rev. 4.1 9.2.3.2 Miscellaneous register Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 $000C POR INTP INTN INTE... A-2 Register outline Register name Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Port A data...) $0001 Port C data (PORTC) $0002 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined...) $0001 Port C data (PORTC) $0002 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined... EPROM/ECLK control $0007 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 State on reset bit 0 EPPT(1) ELAT EPGM... (OPTR) Address Options (OPTR)(1) bit 7 $1EFE bit 6 bit 5 EPP 0 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset RTIM...) $0001 Port C data (PORTC) $0002 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined...) $0001 Port C data (PORTC) $0002 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined... Address EPROM/EEPROM/ECLK control bit 7 $0007 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset E6LAT... Address Mask option register (MOR)(1) bit 7 $3DFE bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset RTIM...) Address Options (OPTR)(1) bit 7 bit 6 bit 5 bit 4 $0100 bit 3 bit 2 State on reset bit 1 bit 0 EE1P SEC Not... Address EPROM/EEPROM/ECLK control bit 7 $0007 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset E6LAT... Address Mask option register (MOR)(1) bit 7 $3DFE bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset RTIM...) Address Options (OPTR)(1) bit 7 bit 6 bit 5 bit 4 $0100 bit 3 bit 2 State on reset bit 1 bit 0 EE1P SEC Not... Mask option register (MOR)(1) bit 7 bit 6 y r a in bit 5 $7FDE bit 4 bit 3 bit 2 bit 1 bit 0 State on reset RTIM...